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ADS1282HPW Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1282HPW Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 59 page  SCLK DIN DOUT t SCLK t SPWH t SCDL t DIST t DIHD t SPWL t SCDL t DOHD t DOPD 11 ADS1282-HT www.ti.com SBAS446H – DECEMBER 2009 – REVISED FEBRUARY 2016 Product Folder Links: ADS1282-HT Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 7.8 Reset Timing Requirements See Figure 48 for timing diagram. MIN MAX UNIT tCRHD CLK to RESET hold time 10 ns tRCSU RESET to CLK setup time 10 ns tRST RESET low 2 1 / ƒCLK tDR Time for data ready 62.98046875 / ƒDATA + 468 / ƒCLK s (1) Load on DOUT = 20 pF || 100 k Ω. 7.9 Read Data Timing Requirements MIN MAX UNIT tDDPD DRDY to valid MSB on DOUT propagation delay (see Figure 54)(1) 100 ns tDR Time for new data after data read command (see Figure 55) 0 1 ƒDATA (1) At DC. See Figure 42. 7.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Group delay(1) Minimum phase filter 5 / ƒDATA s Linear phase filter 31 / ƒDATA Settling time (latency) Minimum phase filter 62 / ƒDATA s Linear phase filter 62 / ƒDATA (1) Load on M0 and M1 = 20 pF || 100 k Ω. 7.11 Modulator Switching Characteristics See Figure 56. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tMCD0, 1 MCLK rising edge to M0, M1 valid propagation delay(1) 100 ns tCMD CLK rising edge (after SYNC rising edge) to MCLK rising edge CMD 5 1/ƒCLK tCSHD CLK to SYNC hold time to not latch on CLK edge 10 ns tSCSU SYNC to CLK setup time to latch on CLK edge 10 ns tSYMD SYNC to stable bit stream 16 1/ƒMOD Figure 1. Timing Diagram |
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