ADC12191CIVT datasheet(7/16 Pages) NSC

No. de pieza	ADC12191CIVT

Descripción Electrónicos	12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold

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Fabricante Electrónico	NSC [National Semiconductor (TI)]

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AC Electrical Characteristics (Continued)

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA,VD or VD I/O), the current at that pin should be limited

to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to

two.

Note 4: The absolute maximum junction temperatures (TJmax) for this device is 150˚C. The maximum allowable power consumption is dictated by TJmax, the

junction-to-ambient thermal resistance (

θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA )/θJA. In the 32-pin

TQFP,

θJA is 74˚C/W, so PDMAX = 1,689 mW at 25˚C and 1,013 mW at the maximum operating ambient temperature of 75˚C. Note that the power consumption of

this device under normal operation will typically be about 255 mW (typical power consumption + 20 mW TTL output loading). The values for maximum power con-

sumption listed above will be reached only when the ADC12191 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power

supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5k

Ω resistor. Machine model is 220 pf discharged through ZERO Ohms.

Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5V above VA or to 5V below GND will not damage this device, provided current

is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 4.75V,

the full-scale input voltage must be

≤4.85V to ensure accurate conversions.

Note 8: To guarantee accuracy, it is required that |VA -VD| ≤ 100mV and separate bypassed capacitors are used at each power supply pin.

Note 9: With the test condition for VREF = +2.0V, the 12-bit LSB is 488µV.

Note 10: Typical figures are at TA =TJ = 25˚C, and represent most likely parametric norms.

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scall and

zero.

Note 13: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced

to 1.4V.

Note 14: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package) or the

LM4041CIZ-ADJ (TO-92 package) bandgap voltage reference is recommended for this application.

DS101040-8

www.national.com

7

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ADC12191CIVT Datasheet(PDF) 7 Page - National Semiconductor (TI)

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