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DAC6311IDCKT Datasheet(PDF) 7 Page - Texas Instruments

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No. de pieza DAC6311IDCKT
Descripción Electrónicos  12-Bit, Low-Power, Single-Channel Digital-to-Analog Converters in SC70 Package
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

DAC6311IDCKT Datasheet(HTML) 7 Page - Texas Instruments

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SCLK
1
16
SYNC
D
IN
DB15
DB0
DB15
t
10
t
6
t
3
t
2
t
1
t
7
t
9
t
5
t
4
t
8
DAC5311, DAC6311, DAC7311
www.ti.com
SBAS442C – AUGUST 2008 – REVISED JULY 2015
7.6 Timing Requirements
at –40°C to 125°C, and AVDD = 2 V to 5.5 V (unless otherwise noted)
(1)
MIN
NOM
MAX
UNIT
AVDD = 2.0 V to 3.6 V
20
f(SCLK)
Serial clock frequency
MHz
AVDD = 3.6 V to 5.5 V
50
AVDD = 2.0 V to 3.6 V
50
t1
SCLK cycle time
ns
AVDD = 3.6 V to 5.5 V
20
AVDD = 2.0 V to 3.6 V
25
t2
SCLK high time
ns
AVDD = 3.6 V to 5.5 V
10
AVDD = 2.0 V to 3.6 V
25
t3
SCLK low time
ns
AVDD = 3.6 V to 5.5 V
10
AVDD = 2.0 V to 3.6 V
0
t4
SYNC to SCLK rising edge setup time
ns
AVDD = 3.6 V to 5.5 V
0
AVDD = 2.0 V to 3.6 V
5
t5
Data setup time
ns
AVDD = 3.6 V to 5.5 V
5
AVDD = 2.0 V to 3.6 V
4.5
t6
Data hold time
ns
AVDD = 3.6 V to 5.5 V
4.5
AVDD = 2.0 V to 3.6 V
0
t7
SCLK falling edge to SYNC rising edge
ns
AVDD = 3.6 V to 5.5 V
0
AVDD = 2.0 V to 3.6 V
50
t8
Minimum SYNC high time
ns
AVDD = 3.6 V to 5.5 V
20
AVDD = 2.0 V to 3.6 V
100
t9
16th SCLK falling edge to SYNC falling edge
ns
AVDD = 3.6 V to 5.5 V
100
AVDD = 2.0 V to 3.6 V
15
SYNC rising edge to 16th SCLK falling edge
t10
ns
(for successful SYNC interrupt)
AVDD = 3.6 V to 5.5 V
15
(1)
All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH) / 2.
Figure 1. Serial Write Operation
Copyright © 2008–2015, Texas Instruments Incorporated
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Product Folder Links: DAC5311 DAC6311 DAC7311


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