ADN2913 datasheet(4/37 Pages) AD

No. de pieza	ADN2913

Descripción Electrónicos	Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

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ADN2913

Data Sheet

Rev. A | Page 4 of 37

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY VOLTAGE

VCC

1.14

1.2

1.26

V

VDD

2.97

3.3

3.63

V

VCC1

1.62

1.8

3.63

V

POWER SUPPLY CURRENT

Limiting amplifier mode, clock output enabled

VCC

1.25 Gbps

277.1

311.0

mA

3.125 Gbps

256.2

288.3

mA

4.25 Gbps

270.1

304.0

mA

6.144 Gbps

303.1

340.4

mA

8GFC,2 JTSPAT

319.1

359.5

mA

VDD

1.25 Gbps

7.24

8.28

mA

3.125 Gbps

7.21

8.21

mA

4.25 Gbps

7.23

8.33

mA

6.144 Gbps

7.26

8.17

mA

8GFC,2 JTSPAT

7.20

8.1

mA

VCC1

1.25 Gbps

35.6

46.8

mA

3.125 Gbps

19.0

24.1

mA

4.25 Gbps

22.2

28.2

mA

6.144 Gbps

19.4

24.6

mA

8GFC,2 JTSPAT

22.2

28.4

mA

TOTAL POWER DISSIPATION

Clock Output Enabled

Limiting amplifier mode, 1.25 Gbps

420.4

mW

Limiting amplifier mode, 3.125 Gbps

365.5

mW

Limiting amplifier mode, 4.25 Gbps

388

mW

Limiting amplifier mode, 6.144 Gbps

422.5

mW

Limiting amplifier mode, 8GFC,2 JTSPAT

446.6

mW

Clock Output Disabled

Equalizer mode, 8.5 Gbps

352

mW

Limiting amplifier mode, 6.144 Gbps

380

mW

0 dB EQ mode, 622 Mbps

340

mW

OPERATING TEMPERATURE RANGE

−40

+85

°C

1 See Figure 34.

2 Fibre Channel Physical Interface-4 standard, FC-PI-4, Rev 8.00, May 21, 2008.

3 When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 100 Ω differential input termination

of the ADN2913 input stage.

4 This typical acquisition specification applies to all selectable reference clock frequencies in the range of 11.05 MHz to 176.8 MHz.

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