 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADN2913 Datasheet(PDF) 6 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADN2913 Datasheet(HTML) 6 Page - Analog Devices |
|
|
6 / 37 page  ADN2913 Data Sheet Rev. A | Page 6 of 37 Parameter Test Conditions/Comments Min Typ Max Unit OC-3 30 Hz 50.0 UI p-p 300 Hz 24.0 UI p-p 6500 Hz 14.4 UI p-p 65 kHz 0.80 UI p-p 1.3 MHz 0.61 UI p-p 1 Jitter transfer bandwidth is programmable by adjusting TRANBW[2:0] in the DPLLA register (Address 0x10). 2 Fibre Channel Physical Interface-4 standard, FC-PI-4, Rev 8.00, May 21, 2008. 3 Conditions of FC-PI-4, Rev 8.00, Table 27, 800-DF-EL-S apply. 4 Must have zero errors during the tests for an interval of time that is ≤10−12 BER to pass the tests. OUTPUT AND TIMING SPECIFICATIONS TA = TMIN to TMAX, VCC = VCCMIN to VCCMAX, VCC1 = VCC1MIN to VCC1MAX, VDD = VDDMIN to VDDMAX, VEE = 0 V, input data pattern: PRBS 223 − 1, ac-coupled to 100 Ω differential termination load, I2C register default settings, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit CML OUTPUT CHARACTERISTICS Data Differential Output Swing 8GFC,1 DATA_SWING[3:0] setting = 0xC (default) 540 600 666 mV p-p 8GFC,1 DATA_SWING[3:0] setting = 0xF (maximum) 662 725 778 mV p-p 8GFC,1 DATA_SWING[3:0] setting = 0x4 (minimum 190 214 245 mV p-p Clock Differential Output Swing 8GFC,1 CLOCK_SWING[3:0] setting = 0xC (default) 426 518 588 mV p-p 8GFC,1 CLOCK_SWING[3:0] setting = 0xF (maximum) 489 603 680 mV p-p 8GFC, CLOCK_SWING[3:0] setting = 0x4 (minimum) 166 213 245 mV p-p Output High Voltage VOH, dc-coupled VCC − 0.05 VCC − 0.025 VCC V Output Low Voltage VOL, dc-coupled VCC − 0.36 VCC − 0.325 VCC − 0.29 V CML OUTPUT TIMING CHARACTERISTICS Rise Time 20% to 80%, at 8GFC,1 DATOUTN/DATOUTP 20.4 33.1 44 ps 20% to 80%, at 8GFC,1 CLKOUTN/CLKOUTP 23.1 29.7 35.8 ps Fall Time 80% to 20%, at 8GFC,1 DATOUTN/DATOUTP 23 34.2 46.8 ps 80% to 20%, at 8GFC,1 CLKOUTN/CLKOUTP 25 31.3 37.1 ps Setup Time, Full Rate Clock tS (see Figure 2) 0.5 UI Hold Time, Full Rate Clock tH (see Figure 2) 0.5 UI Setup Time, Half Rate/DDR Clock tS (see Figure 3) 0.5 UI Hold Time, Half Rate/DDR Clock tH (see Figure 3) 0.5 UI I2C INTERFACE DC CHARACTERISTICS LVTTL Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input Current VIN = 0.1 × VDD or VIN = 0.9 × VDD −10.0 +10.0 μA Output Low Voltage VOL, IOL = 3.0 mA 0.4 V I2C INTERFACE TIMING See Figure 22 SCK Clock Frequency 400 kHz SCK Pulse Width High tHIGH 600 ns SCK Pulse Width Low tLOW 1300 ns Start Condition Hold Time tHD;STA 600 ns Start Condition Setup Time tSU;STA 600 ns Data Setup Time tSU;DAT 100 ns Data Hold Time tHD;DAT 300 ns SCK/SDA Rise/Fall Time tR/tF 20 + 0.1 Cb2 300 ns Stop Condition Setup Time tSU;STO 600 ns Bus Free Time Between Stop and Start Conditions tBUF 1300 ns |
Número de pieza similar - ADN2913 |
|
Descripción similar - ADN2913 |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
