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AD7091R-8BCPZ-RL7 Datasheet(PDF) 10 Page - Analog Devices |
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AD7091R-8BCPZ-RL7 Datasheet(HTML) 10 Page - Analog Devices |
10 / 42 page AD7091R-2/AD7091R-4/AD7091R-8 Data Sheet Rev. C | Page 10 of 42 Pin No. Mnemonic Description TSSOP LFCSP 18 16 SCLK Serial Clock. This pin acts as the serial clock input. 19 17 CONVST Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the track-and-hold mode into hold mode and initiates a conversion. 20 18 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Connect decoupling capacitors between VDRIVE and GND. Typical recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and may be different to the voltage range at VDD. Not applicable 21 EPAD Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be soldered to GND. |
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