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AD9652-310EBZ Datasheet(PDF) 11 Page - Analog Devices

No. de pieza AD9652-310EBZ
Descripción Electrónicos  16-Bit, 310 MSPS, 3.3 V/1.8 V Dual Analog-to-Digital Converter (ADC)
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9652-310EBZ Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD9652
Rev. A | Page 11 of 36
Pin No.
Mnemonic
Type
Description
J3
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
J4
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
J5
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
J6
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
J7
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
J9
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
J10
DRGND
Digital Ground
Digital and Output Driver Ground Reference.
ADC Analog
A9
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
A8
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
A4
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
A5
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
A2
VCM
Output
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 μF capacitor.
A1
RBIAS
Output
External Bias Resister Connection. A 10 kΩ resister must be
connected between this pin and analog ground (AGND).
A12
VREF
Input/Output
Voltage Reference Input/Output.
A11
SENSE
Input
Reference Mode Selection (See Table 12).
E1
CLK+
Input
ADC Clock Input (True).
D1
CLK−
Input
ADC Clock Input (Complement).
Digital Inputs
F1
TEST
Input
Pull-Down. Unused digital input, pull to ground through a 50 Ω
resistor.
G1
SYNC
Input
Digital Input Clock Synchronization Pin. Tie low if unused.
H1
PDWN
Input
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-down
or standby (see Register 0x08 in Table 17).
Digital Outputs
J2
D0+
Output
Channel A/Channel B LVDS Output Data 0 (True, LSB).
J1
D0−
Output
Channel A/Channel B LVDS Output Data 0 (Complement, LSB).
K2
D1+
Output
Channel A/Channel B LVDS Output Data 1 (True).
K1
D1−
Output
Channel A/Channel B LVDS Output Data 1 (Complement).
L1
D2+
Output
Channel A/Channel B LVDS Output Data 2 (True).
M1
D2−
Output
Channel A/Channel B LVDS Output Data 2 (Complement).
L2
D3+
Output
Channel A/Channel B LVDS Output Data 3 (True).
M2
D3−
Output
Channel A/Channel B LVDS Output Data 3 (Complement).
L3
D4+
Output
Channel A/Channel B LVDS Output Data 4 (True).
M3
D4−
Output
Channel A/Channel B LVDS Output Data 4 (Complement).
L4
D5+
Output
Channel A/Channel B LVDS Output Data 5 (True).
M4
D5−
Output
Channel A/Channel B LVDS Output Data 5 (Complement).
L5
D6+
Output
Channel A/Channel B LVDS Output Data 6 (True).
M5
D6−
Output
Channel A/Channel B LVDS Output Data 6 (Complement).
L6
D7+
Output
Channel A/Channel B LVDS Output Data 7 (True).
M6
D7−
Output
Channel A/Channel B LVDS Output Data 7 (Complement).
L7
D8+
Output
Channel A/Channel B LVDS Output Data 8 (True).
M7
D8−
Output
Channel A/Channel B LVDS Output Data 8 (Complement).
L8
D9+
Output
Channel A/Channel B LVDS Output Data 9 (True).
M8
D9−
Output
Channel A/Channel B LVDS Output Data 9 (Complement).
L9
D10+
Output
Channel A/Channel B LVDS Output Data 10 (True).
M9
D10−
Output
Channel A/Channel B LVDS Output Data 10 (Complement).
L10
D11+
Output
Channel A/Channel B LVDS Output Data 11 (True).
M10
D11−
Output
Channel A/Channel B LVDS Output Data 11 (Complement).
L11
D12+
Output
Channel A/Channel B LVDS Output Data 12 (True).
M11
D12−
Output
Channel A/Channel B LVDS Output Data 12 (Complement).


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