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AD9691BCPZ-1250 Datasheet(PDF) 5 Page - Analog Devices |
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AD9691BCPZ-1250 Datasheet(HTML) 5 Page - Analog Devices |
5 / 72 page Data Sheet AD9691 Rev. 0 | Page 5 of 72 Parameter1 Temperature Min Typ Max Unit WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz 25°C −87 dBFS fIN = 170 MHz Full −84 −72 dBFS fIN = 340 MHz 25°C −77 dBFS fIN = 450 MHz 25°C −72 dBFS fIN = 750 MHz 25°C −73 dBFS fIN = 985 MHz 25°C −72 dBFS fIN = 1205 MHz 25°C −66 dBFS fIN = 1600 MHz 25°C −66 dBFS fIN = 1950 MHz 25°C −69 dBFS WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz 25°C −93 dBFS fIN = 170 MHz Full −81 −76 dBFS fIN = 340 MHz 25°C −79 dBFS fIN = 450 MHz 25°C −81 dBFS fIN = 750 MHz 25°C −77 dBFS fIN = 985 MHz 25°C −76 dBFS fIN = 1205 MHz 25°C −72 dBFS fIN = 1600 MHz 25°C −72 dBFS fIN = 1950 MHz 25°C −73 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz, Buffer Current Setting = 3.5× 25°C 82 dBFS fIN1 = 449 MHz, fIN2 = 452 MHz, Buffer Current Setting = 6.5× 25°C 78 dBFS CHANNEL ISOLATION/CROSSTALK4 25°C 95 dB FULL POWER BANDWIDTH5 25°C 1.5 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 10 for the recommended settings for full-scale voltage and buffer current control. 4 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with the circuit shown in Figure 41. DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 600 1200 1800 mV p-p Input Common-Mode Voltage Full 0.85 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF SYSTEM REFERENCE INPUTS (SYSREF+, SYSREF−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance (Differential) Full 2.5 pF |
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