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ADM1278-1AACPZ Datasheet(PDF) 9 Page - Analog Devices |
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ADM1278-1AACPZ Datasheet(HTML) 9 Page - Analog Devices |
9 / 61 page Data Sheet ADM1278 Rev. A | Page 9 of 61 tLOW tBUF tHD;DAT tSU;DAT tSU;STA tHD;STA tHIGH tR tF tSU;STO P S S P VIH VIL VIH VIL SCL SDA Figure 2. Serial Bus Timing Diagram SPI TIMING CHARACTERISTICS (ADM1278-2) Table 5. Parameter Description Min Typ Max Unit Test Conditions/Comments tS1 SPI_SS falling edge to MCLK rising edge setup time 50 ns tHIGH1 MCLK high time 180 ns tLOW1 MCLK low time 180 ns tCLK1 MCLK cycle time 1 μs tH1 Hold time between SPI_SS and MCLK 1 μs tV Hold time between new data valid and MCLK falling edge 110 260 ns Track capacitance = 120 pF; IOL = 4 mA tON SPI_SS falling edge to MDAT active time 130 240 ns Track capacitance = 120 pF; IOL = 4 mA tOFF Bus relinquish time after SPI_SS rising edge 130 280 ns Track capacitance = 120 pF; IOL = 4 mA 1 Guaranteed by design, but not production tested. SPI_SS MCLK MDAT tS 1 79 78 MSB LSB 23 tHIGH tLOW tON DON’T CARE tCLK tH tOFF tV DON’T CARE Figure 3. SPI Timing Diagram |
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