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AD977BR Datasheet(PDF) 9 Page - Analog Devices |
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AD977BR Datasheet(HTML) 9 Page - Analog Devices |
9 / 24 page AD977/AD977A –9– REV. D normally low or normally high when inactive. In the case of the discontinuous clock, the AD977/AD977A can be configured to either generate or not generate a SYNC output (with a continu- ous clock a SYNC output will always be produced). Each of the methods will be described in the following sections and are illustrated in Figures 4 through 9. It should be noted that all timing diagrams assume that the receiving device is latching data on the rising edge of the external clock. If the falling edge of DATACLK is used then, in the case of a discon- tinuous clock, one less clock pulse is required than shown in Figures 4 through 7 to latch in a 16-bit word. Note that data is valid on the falling edge of a clock pulse (for t13 greater than t18) and the rising edge of the next clock pulse. The AD977 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion cycle. Normally the occurrence of an incorrect bit decision during a conversion cycle is irreversible. This error occurs as a result of noise during the time of the decision or due to insufficient settling time. As the AD977/AD977A is perform- ing a conversion it is important that transitions not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion process. For this reason it is recommended that when an external clock is being provided it be a discontinu- ous clock that is not toggling during the time that BUSY is low or, more importantly, that it does not transition during the latter half of BUSY low. EXTERNAL DISCONTINUOUS CLOCK DATA READ AFTER CONVERSION NO SYNC OUTPUT GENERATED Figure 4 illustrates the method by which data from conversion “n” can be read after the conversion is complete using a discon- tinuous external clock without the generation of a SYNC output. After a conversion is complete, indicated by BUSY returning high, the result of that conversion can be read while CS is Low and R/C is high. In this mode CS can be tied low. The MSB will be valid on the first falling edge and the second rising edge of DATACLK. The LSB will be valid on the 16th falling edge and the 17th rising edge of DATACLK. A mini- mum of 16 clock pulses are required for DATACLK if the receiving device will be latching data on the falling edge of DATACLK. A minimum of 17 clock pulses are required for DATACLK if the receiving device will be latching data on the rising edge of DATACLK. Approximately 40 ns after the 17th rising edge of DATACLK (if provided) the DATA output pin will reflect the state of the TAG input pin during the first rising edge of DATACLK. The advantage of this method of reading data is that it is not being clocked out during a conversion and therefore conversion performance is not degraded. When reading data after the conversion is complete, with the highest frequency permitted for DATACLK (15.15 MHz), and with the AD977A, the maximum possible throughput is approxi- mately 195 kHz and not the rated 200 kHz. For details on use of the TAG input with this mode see the Use of the Tag Feature section. BUSY R/C EXT DATACLK t13 t18 BIT 15 (MSB) BIT 14 12 DATA SYNC t14 t12 0 3 14 15 16 t1 t2 t24 t21 BIT 13 BIT 1 BIT 0 (LSB) TAG 0 TAG 1 t23 TAG 0 TAG 1 TAG 2 TAG 3 TAG 15 TAG 16 TAG 17 t18 TAG 18 TAG Figure 4. Conversion and Read Timing Using an External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low) |
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