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ADSP-21583 Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-21583 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 168 page  Preliminary Technical Data Rev. PrF | Page 7 of 168 | February 2016 ADSP-SC582/583/584/587/589/ADSP-21583/584/587 L1 Memory The ADSP-SC58x/ADSP-2158x memory structure is shown in Figure 5 on Page 8. Each SHARC+ core has a tightly coupled Level 1 (L1) SRAM of up to 5 Mbits. Each SHARC+ core can access code and data in a single cycle from this memory space. The ARM Cortex-A5 core can also access these memory spaces with multi-cycle accesses. In the SHARC+ core private address space, both cores have their own L1 memory. SHARC+ core MMR address space is 0x 0000 0000-0x0003 FFFF in Normal Word (32-bit). Each block can be configured for different combinations of code and data storage. Of the 5M bits SRAM, up to 1024K bits can be configured for DM, PM, and instruction cache. Each memory block supports single cycle, independent accesses by the core processor and I/O pro- cessor. The memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor in a single cycle. The proces- sor’s SRAM can be configured as a maximum of 160K words of 32-bit data, 320K words of 16-bit data, 106.7K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 M bits. All of the memory can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on chip. Conversion between the 32-bit floating-point and 16-bit float- ing-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The system configuration is flexible, but a configuration is 512K bits DM, 128K bits PM, and 128K bits of cache, with the remaining L1 memory configured as SRAM is typical. Each addressable memory space outside the L1 memory can be accessed either directly or via cache. Figure 4. SHARC+ SIMD Core Block Diagram S SIMD Core + 11-STAGE PROGRAM SEQUENCER PM ADDRESS 32 PM DATA 64 DM DATA 64 DM ADDRESS 32 DAG1 16 × 32 MRF 80-BIT ALU MULTIPLIER SHIFTER PEX DATA REGISTER Rx 16 × 40-BIT DMD/PMD 64 ASTATx STYKx ASTATy STYKy PEY DATA REGISTER Sx 16 × 40-BIT MRB 80-BIT MSB 80-BIT MSF 80-BIT DAG2 16 × 32 ALU MULTIPLIER SHIFTER DATA SWAP SYSTEM I/F USTAT PX PM ADDRESS 24 PM DATA 48 DEBUG TRACE FLAGS CEC BTB BP CONFLICT CACHE TO IMIF |
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