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GA20JT12-263 Datasheet(PDF) 8 Page - GeneSiC Semiconductor, Inc.

No. de Pieza. GA20JT12-263
Descripción  OFF Silicon Carbide Junction Transistor
Descarga  12 Pages
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Fabricante  GENESIC [GeneSiC Semiconductor, Inc.]
Página de inicio  http://www.genesicsemi.com/
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GA20JT12-263 Datasheet(HTML) 8 Page - GeneSiC Semiconductor, Inc.

 
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GA20JT12-263
Nov 2015
Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
Pg 8 of 11
Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady on-
state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage
developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow
through the device. The voltage applied to the gate pin should be maintained high enough, above the VGS,sat (see Figure 7) level to counter
these effects.
A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. Turn off can be achieved with VGS = 0 V, however a negative gate voltage VGS may be used in order to
speed up the turn-off transition.
Gate Return Pin
The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver connection to the
GA20JT12-263. Drain currents through the source pin during transient and steady state operation induce an undesirable source voltage in all
power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance,
however the gate return pin allows for decoupling from these source current path effects which results in faster switching and higher efficiency
gate driving.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4
The GA20JT12-263 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate
resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in
on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and low-
side driving, its datasheet provides additional details about this drive topology.
Figure 23: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance
3 of RG = 3.75
Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe
operation of the GA20JT12-263. The steady state current supplied to the gate pin of the GA20JT12-263 with on-board RG = 3.75
Ω, is shown
in Figure 24. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 25.
For the GA20JT12-263, RG must be reduced for ID
≥ ~14 A for safe operation with the GA03IDDJT30-FR4.
For operation at ID
≥ ~14 A, R
G may be calculated from the following equation, which contains the DC current gain hFE and the gate-source
saturation voltage VGS,sat (Figure 7).
����������������,������������������������=�4.7��������−������������������������,�������������������������∗ℎ����������������(��������,����������������)
����������������∗1.5 −0.6Ω
IG
CG2
Gate
Signal
VGH
D1
R4
R1
U1
VGL
VEE
U2
VGL
VEE
VGL
U3
VGH
U4
VEE
C2
C1
VEE
U5
VGL
VEE
U6
CG1
RG1
RG2
R2
R3
C5
C3
C4
C8
C6
C9
C10
+12 V
+12 V
VCC High
VCC High RTN
VCC Low
VCC Low RTN
Signal
Signal RTN
Gate
Source
Voltage Isolation Barrier
GA03IDDJT30-FR4
Gate Driver Board
D
S
G
GR


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