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FM24V01A Datasheet(PDF) 7 Page - Cypress Semiconductor |
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FM24V01A Datasheet(HTML) 7 Page - Cypress Semiconductor |
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7 / 19 page  FM24V01A Document Number: 001-90869 Rev. *H Page 7 of 19 Internally, an actual memory write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using START or STOP condition prior to the 8th data bit. The FM24V01A uses no page buffering. The memory array can be write-protected using the WP pin. Setting the WP pin to a HIGH condition (VDD) will write-protect all addresses. The FM24V01A will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP to a LOW state (VSS) will disable the write protect. WP is pulled down internally. Figure 8 and Figure 9 illustrate a single-byte and multiple-byte write cycles in Fast-mode Plus (Fm+). Figure 10 illustrates a single-byte write cycles in Hs mode Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24V01A uses the internal address latch to supply the address. In a selective read, the user performs a procedure to set the address to a specific value. Current Address & Sequential Read As mentioned in the previous paragraph, the FM24V01A uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to a '1'. This indicates that a read operation is requested. After receiving the complete slave address, the FM24V01A will begin shifting out data from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Note Each time the bus master acknowledges a byte, this indicates that the FM24V01A should read out the next sequential byte. Figure 8. Single-Byte Write S A Slave Address 0 Address MSB A Data Byte A P By Master By F-RAM Start Address & Data Stop Acknowledge Address LSB A Figure 9. Multi-Byte Write Figure 10. Hs-Mode Byte Write S A Slave Address 0 Address MSB A Data Byte A P By Master By F-RAM Start Address & Data Stop Acknowledge Address LSB A Data Byte A S A Slave Address 0 Data Byte A P By Master By F-RAM Start & Enter Hs-mode Address & Data Stop & Exit Hs-mode S 1 Start Acknowledge X X X 1 0 0 0 0 Hs-mode command Address MSB A Address LSB A No Acknowledge |
Número de pieza similar - FM24V01A |
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Descripción similar - FM24V01A |
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