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TPS62001DGS Datasheet(PDF) 9 Page - Texas Instruments

No. de Pieza. TPS62001DGS
Descripción  HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER
Descarga  25 Pages
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Fabricante  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TPS62001DGS Datasheet(HTML) 9 Page - Texas Instruments

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TPS62000, TPS62001, TPS62002, TPS62003
TPS62004, TPS62005, TPS62006, TPS62007, TPS62008
HIGHEFFICIENCY STEPDOWN LOW POWER DCDC CONVERTER
SLVS294C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VI = 3.6 V,
VO = 2.5 V, IO = 300 mA, EN = VIN, ILIM = VIN, TA = −40°C to 85°C (unless otherwise noted) (continued)
power switch and current limit
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
P-channel MOSFET on-resistance
VI = VGS = 3.6 V,
I = 200 mA
200
280
410
m
P-channel MOSFET on-resistance
VI = VGS = 2 V,
I = 200 mA
480
m
rDS(on)
P-channel leakage current
VDS = 5.5 V
1
µA
rDS(on)
N-channel MOSFET on-resistance
VI = VGS = 3.6 V,
IO = 200 mA
200
280
410
m
N-channel MOSFET on-resistance
VI = VGS = 2 V,
IO = 200 mA
500
m
N-channel leakage current
VDS = 5.5 V
1
µA
I(LIM)
P-channel current limit
2.5 V
≤ VI ≤ 5.5 V, ILIM = VIN
800
1200
1600
mA
I(LIM)
P-channel current limit
2 V
≤ VI ≤ 5.5 V,
ILIM = GND
390
600
900
mA
VIH
ILIM high-level input voltage
1.3
V
VIL
ILIM low-level input voltage
0.4
V
Ilkg
ILIM input leakage current
ILIM = GND or VIN
0.01
0.1
µA
power good output (see Note 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(PG)
Power good threshold
Feedback voltage falling
88%
VO
92%
VO
94%
VO
V
Power good hysteresis
2.5% VO
V
VOL
PG output low voltage
V(FB) = 0.8 × VO nominal, I(sink) = 10 µA
0.3
V
Ilkg
PG output leakage current
V(FB) = VO nominal
0.01
1
µA
Minimum supply voltage for valid power good signal
1.2
V
NOTE 3: Power good is not valid for the first 100
µs after EN goes high. Please refer to the application section for more information.
oscillator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fs
Oscillator frequency
500
750
1000
kHz
f(SYNC)
Synchronization range
CMOS-logic clock signal on SYNC pin
500
1000
kHz
VIH
SYNC high level input voltage
1.3
V
VIL
SYNC low level input voltage
0.4
V
Ilkg
SYNC input leakage current
SYNC = GND or VIN
0.01
0.1
µA
Duty cycle of external clock signal
20%
60%


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