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COP888CF Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP888CF
Descripción  8-Bit CMOS ROM Based Microcontrollers with 4k Memory and A/D Converter
Descarga  44 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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COP888CF Datasheet(HTML) 6 Page - National Semiconductor (TI)

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DC Electrical Characteristics 988CF: (Continued)
0˚C
≤ T
A ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
15
mA
All others
3mA
Maximum Input Current
T
A = 25˚C
±100
mA
without Latchup (Note 7)
RAM Retention Voltage, V
r
500 ns Rise
2
V
and Fall Time (Min)
Input Capacitance
7pF
Load Capacitance on D2
1000
pF
Note 2: Rate of voltage change must be less then 0.5 V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured as
outputs and set high. The D port set to zero. The A/D is disabled. VREF is tied to AGND (effectively shorting the Reference resistor). The clock monitor is disabled.
A/D Converter Specifications
V
CC = 5V ±10% (VSS − 0.050V) ≤ Any Input ≤ (VCC + 0.050V)
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
Bits
Reference Voltage Input
AGND = 0V
3
V
CC
V
Absolute Accuracy
V
REF = VCC
±1
LSB
Non-Linearity
V
REF = VCC
Deviation from the
±12
LSB
Best Straight Line
Differential Non-Linearity
V
REF = VCC
±12
LSB
Input Reference Resistance
1.6
4.8
k
Common Mode Input Range (Note 8)
AGND
V
REF
V
DC Common Mode Error
±14
LSB
Off Channel Leakage Current
1
µA
On Channel Leakage Current
1
µA
A/D Clock Frequency (Note 6)
0.1
1.67
MHz
Conversion Time (Note 5)
12
A/D Clock
Cycles
Note 5: Conversion Time includes sample and hold time.
Note 6: See Prescaler description.
Note 7: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resis-
tance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 8: For VIN(−)≥VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog
input voltages below ground or above the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode
to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means
that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input
voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading. The voltage at any analog input
should be −0.3V to VCC +0.3V.
www.national.com
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