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COP888EK Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP888EK
Descripción  8-Bit CMOS ROM Based Microcontrollers with 8k Memory, Comparator, and Single-slope A/D Capability
Descarga  46 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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COP888EK Datasheet(HTML) 6 Page - National Semiconductor (TI)

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DC Electrical Characteristics 98xEK: (Continued)
0˚C
≤ T
A ≤ + 70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Input Capacitance
7pF
Load Capacitance on D2
1000
pF
AC Electrical Characteristics 98xEK:
0˚C
≤ T
A≤ + 70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
c)
Crystal, Resonator,
4.0V
≤ V
CC ≤ 6.0V
1.0
DC
µs
2.5V
≤ V
CC < 4.0V
2.5
DC
µs
R/C Oscillator
4.0V
≤ V
CC ≤ 6.0V
3.0
DC
µs
2.5V
≤ V
CC < 4.0V
7.5
DC
µs
Inputs
t
SETUP
4.0V
≤ V
CC ≤ 6.0V
200
ns
2.5V
≤ V
CC < 4.0V
500
ns
t
HOLD
4.0V
≤ V
CC ≤ 6.0V
60
ns
2.5V
≤ V
CC < 4.0V
150
ns
Output Propagation Delay (Note 7)
R
L = 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK
4.0V
≤ V
CC ≤ 6.0V
0.7
µs
2.5V
≤ V
CC < 4.0V
1.75
µs
All Others
4.0V
≤ V
CC ≤ 6.0V
1
µs
2.5V
≤ V
CC < 4.0V
2.5
µs
MICROWIRESetup Time (t
UWS) (Note 7)
V
CC ≥ 4.0V
20
ns
MICROWIRE Hold Time (t
UWH) (Note 7)
V
CC ≥ 4.0V
56
ns
MICROWIRE Output Propagation Delay (t
UPD)VCC ≥ 4.0V
220
ns
Input Pulse Width (Note 8)
Interrupt Input High Time
1.0
t
c
Interrupt Input Low Time
1.0
t
c
Timer 1, 2, 3 Input High Time
1.0
t
c
Timer 1, 2, 3 Input Low Time
1.0
t
c
Reset Pulse Width
1.0
µs
Note 2: tc = Instruction Cycle Time
Note 3: Maximum rate of voltage change must be < 0.5 V/ms.
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing nor
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC;
clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crystal
clock mode.
Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
cludes ESD transients.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8: Parameter characterized but not tested.
www.national.com
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