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COP888XG Datasheet(PDF) 12 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de pieza COP888XG
Descripción Electrónicos  8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory, Comparators and USART
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Fabricante Electrónico  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP888XG Datasheet(HTML) 12 Page - National Semiconductor (TI)

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AC Electrical Characteristics 68xCS and 68xxG:
−55˚C
≤ T
A ≤ +125˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t
c)
Crystal, Resonator
V
CC ≥ 4.5V
1.0
DC
µs
R/C Oscillator
68xCS & 68xEG only)
V
CC ≥ 4.5V
3.0
DC
µs
Inputs
t
SETUP
V
CC ≥ 4.5V
200
ns
t
HOLD
V
CC ≥ 4.5V
60
ns
Output Propagation Delay
R
L = 2.2k, CL = 100 pF
t
PD1,tPD0
SO, SK
V
CC ≥ 4.5V
0.7
µs
All Others
V
CC ≥ 4.5V
1
µs
MICROWIRESetup Time (t
UWS) (Note 10)
20
ns
MICROWIRE Hold Time (t
UWH) (Note 10)
56
ns
MICROWIRE Output Propagation Delay (t
UPD)
220
ns
Input Pulse Width (Note 11)
Interrupt Input High Time
1
t
c
Interrupt Input Low Time
1
t
c
Timer 1, 2, 3 Input High Time
1
t
c
Timer 1, 2, 3 Input Low Time
1
t
c
Reset Pulse Width
1
µs
Note 6: Maximum rate of voltage change must be less than 0.5 V/ms.
Note 7: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 8: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of IDD HALT is done with device neither sourcing or
sinking current; with L, C, and G0–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC;
clock monitor and comparators disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT in crys-
tal clock mode.
Note 9: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current
to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V. WARNING: Voltages in excess of 14V will cause damage to the
pins. This warning excludes ESD transients.
Note 10: Parameter characterized but not tested.
Note 11: tc = Instruction Cycle Time
Comparators AC and DC Characteristics
V
CC = 5V, −40˚C ≤ TA ≤ +85˚C.
Parameter
Conditions
Min
Typ
Max
Units
Input Offset Voltage
0.4V
≤ V
IN ≤ VCC − 1.5V
±10
±25
mV
Input Common Mode Voltage Range
0.4
V
CC − 1.5
V
Voltage Gain
300k
V/V
Low Level Output Current
V
OL = 0.4V
1.6
mA
High Level Output Current
V
OH = 4.6V
1.6
mA
DC Supply Current per Comparator (When Enabled)
250
µA
Response Time
100 mV Overdrive,
1
µs
100 pF Load
www.national.com
12


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