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COP8ACC5 Datasheet(PDF) 32 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP8ACC5
Descripción  8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
Descarga  41 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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COP8ACC5 Datasheet(HTML) 32 Page - National Semiconductor (TI)

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Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
Contents
S/ADD REG
0000 to 006F
On-Chip RAM bytes (112
bytes)
0070 to 007F
Unused RAM Address Space
(Reads As All Ones)
xx80 to xxAF
Unused RAM Address Space
(Reads Undefined Data)
xxB0
Reserved
XXB1
Reserved
xxB2
Reserved
xxB3
Reserved
xxB4
Reserved
xxB5
Reserved
xxB6
Reserved
xxB7
Comparator Select Register
(CMPSL)
xxB8 to xxBF
Reserved
xxC0
Reserved
xxC1
Reserved
xxC2
Reserved
xxC3
Reserved
xxC4
Reserved
xxC5
Reserved
xxC6
Reserved
xxC7
WATCHDOG Service Register
(Reg:WDSVR)
xxC8
MIWU Edge Select Register
(Reg:WKEDG)
xxC9
MIWU Enable Register
(Reg:WKEN)
xxCA
MIWU Pending Register
(Reg:WKPND)
xxCB
Reserved
xxCC
CAPTLO (Capture Timer
Low-Byte)
xxCD
CAPTHI (Capture Timer
High-Byte)
xxCE
CAPCNTL (Capture Timer
Control Register)
xxCF
Idle Timer Control Register
xxD0
Port L Data Register
xxD1
Port L Configuration Register
xxD2
Port L Input Pins (Read Only)
xxD3
Reserved
xxD4
Port G Data Register
xxD5
Port G Configuration Register
xxD6
Port G Input Pins (Read Only)
xxD7
Port I Input Pins (Read Only)
xxD8
Reserved
Address
Contents
S/ADD REG
xxD9
Reserved
xxDA
Reserved
xxDB
Reserved
xxDC
Port D
xxDD to DF
Reserved
xxE0 to xxE5
Reserved
xxE6
Timer T1 Autoload Register
T1RB Lower Byte
xxE7
Timer T1 Autoload Register
T1RB Upper Byte
xxE8
ICNTRL Register
xxE9
MICROWIRE/PLUS Shift
Register
xxEA
Timer T1 Lower Byte
xxEB
Timer T1 Upper Byte
xxEC
Timer T1 Autoload Register
T1RA Lower Byte
xxED
Timer T1 Autoload Register
T1RA Upper Byte
xxEE
CNTRL Control Register
xxEF
PSW Register
xxF0 to xxFB
On-Chip RAM Mapped as
Registers
xxFC
X Register
xxFD
SP Register
xxFE
B Register
xxFF
Reserved
0100-017F
Reserved
Reading memory locations 0070H-007FH (Segment 0) will
return
all
ones.
Reading
unused
memory
locations
0080H-00AFH (Segment 0) will return undefined data. Read-
ing memory locations from other Segments (i.e., Segment 2,
Segment 3,…etc.) will return undefined data.
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or decre-
ment of pointer)
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that au-
tomatically post increments or decrements the B or X regis-
ter after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
www.national.com
32


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