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COP8ACC5 Datasheet(PDF) 33 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP8ACC5
Descripción  8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
Descarga  41 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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COP8ACC5 Datasheet(HTML) 33 Page - National Semiconductor (TI)

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Addressing Modes (Continued)
Immediate
The instruction contains an 8-bit immediate field as the oper-
and.
Short Immediate
This addressing mode is used with the Load B Immediate in-
struction. The instruction contains a 4-bit immediate field as
the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new pro-
gram location. JP has a range from −31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “pages” when using JP, since all 15
bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion up to 32k in the program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt ser-
vice routine.
Instruction Set
Register and Symbol Definition
Registers
A
8-Bit Accumulator Register
B
8-Bit Address Register
X
8-Bit Address Register
SP
8-Bit Stack Pointer Register
PC
15-Bit Program Counter Register
PU
Upper 7 Bits of PC
PL
Lower 8 Bits of PC
C
1-Bit of PSW Register for Carry
HC
1-Bit of PSW Register for Half Carry
GIE
1-Bit of PSW Register for Global Interrupt
Enable
VU
Interrupt Vector Upper Byte
VL
Interrupt Vector Lower Byte
Symbols
[B]
Memory Indirectly Addressed by B Register
[X]
Memory Indirectly Addressed by X Register
MD
Direct Addressed Memory
Mem
Direct Addressed Memory or [B]
Meml
Direct Addressed Memory or [B] or Immediate
Data
Imm
8-Bit Immediate Data
Reg
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit
Bit Number (0 to 7)
Loaded with
Exchanged with
INSTRUCTION SET
ADD
A,Meml
ADD
A ← A + Meml
ADC
A,Meml
ADD with Carry
A ← A+Meml+C,C ← Carry, HC ← Half Carry
SUBC
A,Meml
Subtract with Carry
A ← A−MemI+C,C ← Carry, HC ← Half Carry
AND
A,Meml
Logical AND
A ← A and Meml
ANDSZ
A,Imm
Logical AND Immed., Skip if Zero
Skip next if (A and Imm) = 0
OR
A,Meml
Logical OR
A ← A or Meml
XOR
A,Meml
Logical EXclusive OR
A ← A xor Meml
IFEQ
MD,Imm
IF EQual
Compare MD and Imm, Do next if MD = Imm
IFEQ
A,Meml
IF EQual
Compare A and Meml, Do next if A = Meml
IFNE
A,Meml
IF Not Equal
Compare A and Meml, Do next if A
≠ Meml
IFGT
A,Meml
IF Greater Than
Compare A and Meml, Do next if A > Meml
IFBNE
#
If B Not Equal
Do next if lower 4 bits of B
≠ Imm
DRSZ
Reg
Decrement Reg., Skip if Zero
Reg ← Reg − 1, Skip if Reg = 0
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