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COP8ACC5 Datasheet(PDF) 12 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP8ACC5
Descripción  8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
Descarga  41 Pages
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Fabricante  NSC [National Semiconductor (TI)]
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COP8ACC5 Datasheet(HTML) 12 Page - National Semiconductor (TI)

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Functional Description
The architecture of the device is a modified Harvard archi-
tecture. With the Harvard architecture, the control store pro-
gram memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own sepa-
rate addressing space with separate address buses. The ar-
chitecture, though based on the Harvard architecture, per-
mits transfer of data from ROM to RAM.
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
C) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC® is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad-
dress 06F with reset.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
The program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID in-
struction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the device vector to program
memory location 0FF Hex.
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, and SP pointers.
The data memory consists of 128 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, B and SP are memory mapped into this space at
address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
The RESET input when pulled low initializes the microcon-
troller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L and G are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedi-
cated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL and
CNTRL-control registers are cleared. The Comparator Se-
lect Register is cleared. The S register is initialized to zero.
The Multi-Input Wakeup registers WKEN and WKEDG are
cleared. Wakeup register WKPND is unknown. The stack
pointer, SP, is initialized to 6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
C clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
C-32 tC clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
Figure 6 should be used
to ensure that the RESET pin is held low until the power sup-
ply to the chip stabilizes.
When the device is held in reset for a long time it will con-
sume high current (typically about 7 mA). This is not true for
the equivalent ROM device (COP8ACC5).
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre-
quency is divided down by 10 to produce the instruction
cycle clock (t
Figure 7 shows the Crystal and R/C Oscillator diagrams.
FIGURE 6. Recommended Reset Circuit

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