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COP8ACC5 Datasheet(PDF) 16 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP8ACC5
Descripción  8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
Descarga  41 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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COP8ACC5 Datasheet(HTML) 16 Page - National Semiconductor (TI)

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Timers (Continued)
Figure 11 shows a block diagram of the timer in Input Cap-
ture mode.
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
T1C3
Timer mode control
T1C2
Timer mode control
T1C1
Timer mode control
T1C0
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
T1PNDA Timer Interrupt Pending Flag
T1ENA
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
T1PNDB Timer Interrupt Pending Flag
T1ENB
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:
Mode
T1C3
T1C2
T1C1
Description
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
1
1
0
1
PWM: T1A Toggle
Autoreload RA
Autoreload RB
t
C
1
0
0
PWM: No T1A
Toggle
Autoreload RA
Autoreload RB
t
C
2
0
0
0
External Event
Counter
Timer
Underflow
Pos. T1B Edge
Pos. T1A
Edge
0
0
1
External Event
Counter
Timer
Underflow
Pos. T1B Edge
Pos. T1A
Edge
3
0
1
0
Captures:
Pos. T1A Edge
Pos. T1B Edge
t
C
T1A Pos. Edge
or Timer
T1B Pos. Edge
Underflow
1
1
0
Captures:
Pos. T1A
Neg. T1B
t
C
T1A Pos. Edge
Edge or Timer
Edge
T1B Neg. Edge
Underflow
0
1
1
Captures:
Neg. T1A
Neg. T1B
t
C
T1A Neg. Edge
Edge or Timer
Edge
T1B Neg. Edge
Underflow
1
1
1
Captures:
Neg. T1A
Neg. T1B
t
C
T1A Neg. Edge
Edge or Timer
Edge
T1B Neg. Edge
Underflow
HIGH SPEED CAPTURE TIMER
The device provides a 16-bit high-speed capture timer. The
timer consists of a 16-bit up-counter that is clocked with the
device clock input frequency (CKI) and an 8-bit control regis-
ter. The 16-bit counter is mapped as two read/write 8-bit reg-
isters. This timer is specifically designed to be used in con-
junction with the Analog Function Block (comparator, analog
multiplexer, constant current source) to implement a
low-cost, high-resolution, single-slope A/D.
The timer is automatically stopped in the event of a capture
to allow the software to read the timer value. Coming out of
reset the counter is disabled (stopped) and reads all “0”.
Setting the Capture Timer Run bit CAPRUN bit in the Cap-
ture Control Register (CAPCNTL) will start the counter. The
counter will count up until a capture event (negative edge) is
received. Upon a capture the counter will be stopped, the
Capture Pending bit (CAPPND) is set, and the CAPRUN bit
is automatically reset. If capture interrupts are enabled
(CAPIEN=1), the capture event will generate an interrupt.
Setting the CAPRUN bit again by software will start a new
counting cycle. If the Capture Mode bit is reset (CAP-
MOD=0) the capture timer will be automatically initialized to
all “0” with each setting of the CAPRUN bit. If CAPMOD=1
the timer will not be cleared when setting the CAPRUN bit,
thus allowing the user’s software to pre-load the timer regis-
DS012865-12
FIGURE 11. Timer in Input Capture Mode
www.national.com
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