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COP8ACC5 Datasheet(PDF) 22 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No. de Pieza. COP8ACC5
Descripción  8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D
Descarga  41 Pages
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Fabricante  NSC [National Semiconductor (TI)]
Página de inicio  http://www.national.com
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COP8ACC5 Datasheet(HTML) 22 Page - National Semiconductor (TI)

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Interrupts (Continued)
MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable.
Each maskable interrupt has an associated enable bit and
pending flag bit. The pending bit is set to 1 when the interrupt
condition occurs. The state of the interrupt enable bit, com-
bined with the GIE bit determines whether an active pending
flag actually triggers an interrupt. All of the maskable inter-
rupt pending and enable bits are contained in mapped con-
trol registers, and thus can be controlled by the software.
A maskable interrupt condition triggers an interrupt under the
following conditions:
1.
The enable bit associated with that interrupt is set.
2.
The GIE bit is set.
3.
The device is not processing a non-maskable interrupt.
(If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is
completed.)
An interrupt is triggered only when all of these conditions are
met at the beginning of an instruction. If different maskable
interrupts meet these conditions simultaneously, the highest
priority interrupt will be serviced first, and the other pending
interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the
GIE bit are reset to zero. Thus, a maskable interrupt condi-
tion cannot trigger an interrupt until the program enables it by
setting both the GIE bit and the individual enable bit. When
enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be ac-
knowledged. If, at the time an interrupt is enabled, any pre-
vious occurrences of the interrupt should be ignored, the as-
sociated pending bit must be reset to zero prior to enabling
the interrupt. Otherwise, the interrupt may be simply en-
abled; if the pending bit is already set, it will immediately trig-
ger an interrupt. A maskable interrupt is active if its associ-
ated enable and pending bits are set.
An interrupt is an asychronous event which may occur be-
fore, during, or after an instruction cycle. Any interrupt which
occurs during the execution of an instruction is not acknowl-
edged until the start of the next normally executed instruction
is to be skipped, the skip is performed before the pending in-
terrupt is acknowledged.
At the start of interrupt acknowledgment, the following ac-
tions occur:
1.
The GIE bit is automatically reset to zero, preventing any
subsequent maskable interrupt from interrupting the cur-
rent service routine. This feature prevents one maskable
interrupt from interrupting another one being serviced.
2.
The address of the instruction about to be executed is
pushed onto the stack.
3.
The program counter (PC) is loaded with 00FF Hex,
causing a jump to that program memory location.
The device requires seven instruction cycles to perform the
actions listed above.
If the user wishes to allow nested interrupts, the interrupts
service routine may set the GIE bit to 1 by writing to the PSW
register, and thus allow other maskable interrupts to interrupt
the current service routine. If nested interrupts are allowed,
caution must be exercised. The user must write the program
in such a way as to prevent stack overflow, loss of saved
context information, and other unwanted conditions.
The interrupt service routine stored at location 00FF Hex
should use the VIS instruction to determine the cause of the
interrupt, and jump to the interrupt handling routine corre-
sponding to the highest priority enabled and active interrupt.
Alternately, the user may choose to poll all interrupt pending
DS012865-15
FIGURE 14. Interrupt Block Diagram
www.national.com
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