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MC10319 Datasheet(PDF) 9 Page - Motorola, Inc |
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MC10319 Datasheet(HTML) 9 Page - Motorola, Inc |
9 / 20 page MC10319 9 MOTOROLA ANALOG IC DEVICE DATA ICC(A) is nominally 17 mA, and does not vary with clock frequency or with Vin. It does vary linearly with VCC(A). ICC(D) is nominally 90 mA, and is independent of clock frequency. It does vary, however, by 6 to 7 mA as Vin is changed, with the lowest current occurring when Vin = VRT. It varies linearly with VCC(D). VEE is the negative power supply for the comparators, and is to be within the range – 3.0 to – 6.0 V. Additionally, VEE must be at least 1.3 V more negative than VRB. IEE is a nominal – 10 mA, and is independent of clock frequency, Vin, and VEE. For proper operation, the supplies must be bypassed at the IC. A 10 µF tantalum, in parallel with a 0.1 µF ceramic is recommended for each supply to ground. DIGITAL SECTION Clock The Clock input is TTL compatible with a typical frequency range of 0 to 30 MHz. There is no duty cycle limitations, but the minimum low and high times must be adhered to. See Figure 7 for the input current requirements. The conversion sequence is shown in Figure 19, and is as follows: • On the rising edge, the data output latches are latched with old data, and the comparator output latches are released to follow the input signal (Vin). • During the high time, the comparators track the input signal. The data output latches retain the old data. • On the falling edge, the comparator outputs are latched with the data immediately prior to this edge. The conversion to digital occurs within the device, and the data output latches are released to indicate the new data within 20 ns. • During the clock low time, the comparator outputs remain latched, and the data output latches remain transparent. A summary of the sequence is that data present at Vin just prior to the Clock falling edge is digitized and available at the data outputs immediately after that same falling edge. The comparator output latches provide the circuit with an effective sample–and–hold function, eliminating the need for an external sample–and–hold. Enable Inputs The two Enable inputs are TTL compatible, and are used to change the data outputs (D7–D0) from active to 3–state. This capability allows cascading two MC10319s into a 9–bit configuration, flip–flopping two MC10319s into a 50 MHz configuration, connecting the outputs directly to a data bus, multiplexing multiple converters, etc. See the Applications Information section for more details. For the outputs to be active, Pin 19 must be a Logic “1”, and Pin 20 must be a Logic “0”. Changing either input will put the outputs into the high impedance mode. The Enable inputs affect only the state of the outputs – they do not inhibit a conversion. The input current into Pins 19 and 20 is shown in Figure 6, and the input/output timing is shown in Figure 1 and 20. Leaving either pin open is equivalent to a Logic “1”, although good design practice dictates that an input should never be left open. The Overrange output (Pin 3) is not affected by the Enable inputs as it does not have 3–state capability. Outputs The Data outputs are TTL level outputs with high impedance capability. Pin 4 is the MSB (D7), and Pin 21 is the LSB (D0). The eight outputs are active as long as the Enable inputs are true (Pin 19 = high, Pin 20 = low). The timing of the outputs relative to the Clock input and the Enable inputs is shown in Figures 1 and 20. Figures 8 and 9 indicate the output voltage versus load current, while Figure 3 indicates the leakage current when in the high impedance mode. The output code is natural binary, depicted in the table below. The Overrange output (Pin 3) goes high when the input, Vin, is more positive than VRT – 1/2 LSB. This output is always active – it does not have high impedance capability. Besides being used to indicate an input overrange, it is additionally used for cascading two MC10319s to form a 9–bit A/D converter (see Figure 27). Table 1. Output Code I VRT, VRB (V) Output O Input 2.048 V, 0 V + 1.0 V, – 1.0 V + 1.0 V, 0 V Output Code Overrange uVRT – 1/2 LSB u2.044V u0.9961 V u0.9980 V FFH 1 VRT – 1/2 LSB 2.044 V 0.9961 V 0.9980 V FFH 0 ↔ 1 VRT – 1 LSB 2.040 V 0.992 V 0.9961 V FFH 0 VRT – 1–1/2 LSB 2.036 V 0.988 V 0.9941 V FEH ↔ FFH 0 Midpoint 1.024 V 0.000 V 0.5000 V 80H 0 VRB + 1/2 LSB 4.0 mV – 0.9961 V 1.95 mV 00H ↔ 01H 0 tVRB t0 V t– 1.0 V t0 V 00H 0 |
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