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COP888CS Datasheet(PDF) 26 Page - National Semiconductor (TI) |
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COP888CS Datasheet(HTML) 26 Page - National Semiconductor (TI) |
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26 / 53 page  USART (Continued) CHL1, CHL0: These bits select the character frame format. Parity is not included and is generated/verified by hardware. Read/Write, cleared on reset. CHL1 = 0, CHL0 = 0 The frame contains eight data bits. CHL1 = 0, CHL0 = 1 The frame contains seven data bits. CHL1 = 1, CHL0 = 0 The frame contains nine data bits. CHL1 = 1, CHL0 = 1 Loopback Mode selected. Trans- mitter output internally looped back to receiver input. Nine bit framing format is used. ERR: This bit is a global USART error flag which gets set if any or a combination of the errors (DOE, FE, PE) occur. Read only; it cannot be written by software, cleared on reset. RBFL: This bit is set when the USART has received a com- plete character and has copied it into the RBUF register. It is automatically reset when software reads the character from RBUF. Read only; it cannot be written by software, cleared on reset. TBMT: This bit is set when the USART transfers a byte of data from the TBUF register into the TSFT register for trans- mission. It is automatically reset when software writes into the TBUF register. Read only, bit is set to “one” on reset; it cannot be written by software. ENUR-USART Receive Control and Status Register (Address at 0BB) DOE FE PE Reserved RBIT9 ATTN XMTG RCVG (Note 12) Bit 7 Bit 0 Note 12: Bit is reserved for future use. User must set to zero. DOE: Flags a Data Overrun Error. Read only, cleared on read, cleared on reset. DOE = 0 Indicates no Data Overrun Error has been de- tected since the last time the ENUR register was read. DOE = 1 Indicates the occurrence of a Data Overrun Er- ror. FE: Flags a Framing Error. Read only, cleared on read, cleared on reset. FE = 0 Indicates no Framing Error has been detected since the last time the ENUR register was read. FE = 1 Indicates the occurrence of a Framing Error. PE: Flags a Parity Error. Read only, cleared on read, cleared on reset. PE = 0 Indicates no Parity Error has been detected since the last time the ENUR register was read. PE = 1 Indicates the occurrence of a Parity Error. SPARE: Reserved for future use. Read/Write, cleared on re- set. RBIT9: Contains the ninth data bit received when the US- ART is operating with nine data bits per frame. Read only, cleared on reset. ATTN: ATTENTION Mode is enabled while this bit is set. This bit is cleared automatically on receiving a character with data bit nine set. Read/Write, cleared on reset. XMTG: This bit is set to indicate that the USART is transmit- ting. It gets reset at the end of the last frame (end of last Stop bit). Read only, cleared on reset. RCVG: This bit is set high whenever a framing error occurs and goes low when RDX goes high. Read only, cleared on reset. ENUI-USART Interrupt and Clock Source Register (Address at 0BC) STP2 STP78 ETDX SSEL XRCLK XTCLK ERI ETI Bit 7 Bit 0 STP2: This bit programs the number of Stop bits to be trans- mitted. Read/Write, cleared on reset. STP2 = 0 One Stop bit transmitted. STP2 = 1 Two Stop bits transmitted. STP78: This bit is set to program the last Stop bit to be 7/8th of a bit in length. Read/Write, cleared on reset. ETDX: TDX (USART Transmit Pin) is the alternate function assigned to Port L pin L2; it is selected by setting ETDX bit. To simulate line break generation, software should reset ETDX bit and output logic zero to TDX pin through Port L data and configuration registers. Read/Write, cleared on re- set. SSEL: USART mode select. Read/Write, cleared on reset. SSEL = 0 Asynchronous Mode. SSEL = 1 Synchronous Mode. XRCLK: This bit selects the clock source for the receiver section. Read/Write, cleared on reset. XRCLK = 0 The clock source is selected through the PSR and BAUD registers. XRCLK = 1 Signal on CKX (L1) pin is used as the clock. XTCLK: This bit selects the clock source for the transmitter section. Read/Write, cleared on reset. XTCLK = 0 The clock source is selected through the PSR and BAUD registers. XTCLK = 1 Signal on CKX (L1) pin is used as the clock. ERI: This bit enables/disables interrupt from the receiver section. Read/Write, cleared on reset. ERI = 0 Interrupt from the receiver is disabled. ERI = 1 Interrupt from the receiver is enabled. ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset. ETI = 0 Interrupt from the transmitter is disabled. ETI = 1 Interrupt from the transmitter is enabled. Associated I/O Pins Data is transmitted on the TDX pin and received on the RDX pin. TDX is the alternate function assigned to Port L pin L2; it is selected by setting ETDX (in the ENUI register) to one. RDX is an inherent function of Port L pin L3, requiring no setup. The baud rate clock for the USART can be generated on-chip, or can be taken from an external source. Port L pin L1 (CKX) is the external clock I/O pin. The CKX pin can be either an input or an output, as determined by Port L Con- figuration and Data registers (Bit 1). As an input, it accepts a clock signal which may be selected to drive the transmitter and/or receiver. As an output, it presents the internal Baud Rate Generator output. www.national.com 26 |
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