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TPS70448PWP Datasheet(PDF) 6 Page - Texas Instruments |
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TPS70448PWP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 32 page TPS70445, TPS70448, TPS70451, TPS70458, TPS70402 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS307B – SEPTEMBER 2000 – REVISED APRIL 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PG2 timing diagram (assuming VIN1 already powered up) NOTES: A. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. t t PG2 Output VIN2 t VIT+ (see Note A) VOUT2 VIT – (see Note A) Threshold Voltage Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION EN1 6 I Active low enable for VOUT1 EN2 7 I Active low enable for VOUT2 GND 9 Ground GND/HEATSINK 1, 12, 13, 24 Ground/heatsink MR 5 I Manual reset input, active low, pulled up internally NC 4, 17, 20 No connection PG1 19 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage PG2 18 O Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage RESET 8 O Open drain output, SVS (power on reset) signal, active low VIN1 2, 3 I Input voltage of regulator 1 VIN2 10, 11 I Input voltage of regulator 2 VOUT1 22, 23 O Output voltage of regulator 1 VOUT2 14, 15 O Output voltage of regulator 2 VSENSE1/FB1 21 I Regulator 1 output voltage sense/ regulator 1 feedback for adjustable VSENSE2/FB2 16 I Regulator 2 output voltage sense/ regulator 2 feedback for adjustable |
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