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ADC10DV200

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SNAS471A – FEBRUARY 2009 – REVISED APRIL 2013

Timing and AC Characteristics

(1)

(2)

Typical

Units

Symbol

Parameter

Conditions

Limits

(3)

(Limits)

LVDS OUTPUT MODE

Maximum Clock Frequency

200

MHz (max)

DCS On

65

Minimum Clock Frequency

MHz (min)

DCS Off

45

DCS On

1.5

Clock High Time

ns (min)

DCS Off

2.4

DCS On

1.5

Clock Low Time

ns (min)

DCS Off

2.4

5/5.5

Conversion Latency

Clock Cycles

(A/B)

Output Delay of CLK to A-Channel Data

Relative to rising edge of CLK

2.7

1.46

ns (min)

Output Delay of CLK to B-Channel Data

Relative to falling edge of CLK

2.7

1.46

ns (min)

Data Output Setup Time

Relative to DRDY

1.2

0.7

ns (min)

Data Output Hold Time

Relative to DRDY

1.2

0.7

ns (min)

Aperture Delay

0.7

ns

Aperture Jitter

0.3

ps rms

Data-Data Skew

20

470

ps

Maximum Clock Frequency

170

MHz

DCS On

65

Minimum Clock Frequency

MHz

DCS Off

25

DCS On

1.76

Clock High Time

ns

DCS Off

2.82

DCS On

1.76

ns

DCS Off

2.82

Conversion Latency

5.5

Clock Cycles

3.15

ns (min)

Output Delay of CLK to DATA

Relative to falling edge of CLK

4.5

5.81

ns (max)

Relative to DRDY

2.5

1.79

ns (min)

Relative to DRDY

3.4

2.69

ns (min)

Aperture Delay

0.7

ns

Aperture Jitter

0.3

ps rms

(1)

current is limited per Note 4 under the Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes

(2)

(3)

specifications are not ensured.

(4)

(5)

This parameter is specified by design and/or characterization and is not tested in production.

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