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ADC12030 Datasheet(PDF) 11 Page - Texas Instruments

No. de pieza ADC12030
Descripción Electrónicos  12-Bit Plus Sign Serial I/O A/D Converters
Download  52 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADC12030 Datasheet(HTML) 11 Page - Texas Instruments

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ADC12030, ADC12032, ADC12034
ADC12038, ADC12H030, ADC12H032
ADC12H034, ADC12H038
www.ti.com
SNAS080K – JULY 1999 – REVISED MARCH 2013
Timing Characteristics
The following specifications apply for V
+ = V
A+ = VD+ = +5.0 VDC, VREF+ = +4.096 VDC, VREF− = 0 VDC, 12-bit + sign
conversion mode, tr = tf = 3 ns, fCK = fSK = 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03, fCK = fSK =
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω,
fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
(1)
Typical
Limits
Units
Parameter
Test Conditions
(2)
(3)
(Limits)
Hardware Power-Up Time, Time from PD Falling Edge to
tHPU
140
250
µs (max)
EOC Rising Edge
Software Power-Up Time, Time from Serial Data Clock
tSPU
140
250
µs (max)
Falling Edge to EOC Rising Edge
tACC
Access Time Delay from CS Falling Edge to DO Data Valid
20
50
ns (max)
Set-Up Time of CS Falling Edge to Serial Data Clock Rising
tSET-UP
30
ns (min)
Edge
tDELAY
Delay from SCLK Falling Edge to CS Falling Edge
0
5
ns (min)
t1H, t0H
Delay from CS Rising Edge to DO TRI-STATE
RL = 3k, CL = 100 pF
40
100
ns (max)
tHDI
DI Hold Time from Serial Data Clock Rising Edge
5
15
ns (min)
tSDI
DI Set-Up Time from Serial Data Clock Rising Edge
5
10
ns (min)
50
ns (max)
tHDO
DO Hold Time from Serial Data Clock Falling Edge
RL = 3k, CL = 100 pF
25
5
ns (min)
tDDO
Delay from Serial Data Clock Falling Edge to DO Data Valid
35
50
ns (max)
DO Rise Time, TRI-STATE to High
RL = 3k, CL = 100 pF
10
30
ns (max)
tRDO
DO Rise Time, Low to High
RL = 3k, CL = 100 pF
10
30
ns (max)
DO Fall Time, TRI-STATE to Low
RL = 3k, CL = 100 pF
12
30
ns (max)
tFDO
DO Fall Time, High to Low
RL = 3k, CL = 100 pF
12
30
ns (max)
tCD
Delay from CS Falling Edge to DOR Falling Edge
25
45
ns (max)
Delay from Serial Data Clock Falling Edge to DOR Rising
tSD
25
45
ns (max)
Edge
CIN
Capacitance of Logic Inputs
10
pF
COUT
Capacitance of Logic Outputs
20
pF
(1)
Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output
voltage is forced to 1.4V.
(2)
Typical figures are at TJ = TA = 25°C and represent most likely parametric norm.
(3)
Tested limits are specified to AOQL (Average Outgoing Quality Level).
Copyright © 1999–2013, Texas Instruments Incorporated
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Product Folder Links: ADC12030 ADC12032 ADC12034 ADC12038 ADC12H030 ADC12H032 ADC12H034
ADC12H038


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