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ADC16DX370RMER Datasheet(PDF) 4 Page - Texas Instruments |
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ADC16DX370RMER Datasheet(HTML) 4 Page - Texas Instruments |
4 / 77 page AGND S+ S- VA3.0 OVRA/ TRIGRDY VA1.8 VA3.0 80: 80: VA3.0 VA1.2 AGND VA3.0 + - CLKIN+ CLKIN- 50: 0.5V 50: 10k: AGND VA1.2 ADC16DX370 SNVSA18C – APRIL 2014 – REVISED AUGUST 2014 www.ti.com Pin Functions (continued) PIN TYPE OR DIAGRAM DESCRIPTION NAME NUMBER Differential device clock input pins Each pin is internally terminated to a DC bias with a 50- Ω resistor for a 100-Ω total internal differential termination. AC coupling is required for coupling the CLKIN+, CLKIN– 17, 18 clock input to these pins if the clock driver cannot meet the common-mode requirements. Sampling occurs on the rising edge of the differential signal (CLKIN+) − (CLKIN–). SPI chip select pin When this signal is asserted, SCLK is used to clock the input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO CSB 54 pin is high impedance and the input data is ignored. Active low. A 10 k Ω pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2- to 3.0-V CMOS logic levels. Digital ground Must be connected to the same solid ground reference plane under the device to which AGND connects. DGND 25, 46 Digital ground Bypass capacitors connected to the VD1.2 pins must be connected to ground as close to this DGND pins as possible. Over-range detection outputs OVRA, OVRB 44, 43 These pins output the channel A and channel B over- range signals as 1.8-V CMOS logic level outputs. Differential high speed serial data lane pins for channel A These pins must be AC coupled to the receiving SA0+, SA0–, device. The differential trace routing from these pins 38, 39, 36, 37 SA1+, SA1– must maintain a 100- Ω characteristic impedance. In single-lane mode, SA0+ or SAO– is used to transfer data and SA1+ or SA1– is undefined and may be left floating. Differential high speed serial data lane pins for channel B. These pins must be AC coupled to the receiving device. The differential trace routing from these pins SB0+, SB0–, 32, 33, 34, 35 must maintain a 100- Ω characteristic impedance. In SB1+, SB1– single-lane mode, SB0+ or SB0– is used to transfer data and SB1+ and SB1– is undefined and may be left floating. 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: ADC16DX370 |
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