T/H

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

SCLK

CS

SDATA

CONTROL

LOGIC

10

ADC121S021

SNAS305J – JULY 2005 – REVISED MARCH 2016

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9 Detailed Description

9.1 Overview

The ADC121S021 is a low-power, single-channel, 12-bit analog-to-digital converter which is based upon a

successive-approximation register architecture with an internal track-and-hold circuit. It operates with a

single

‑supply voltage that can range from 2.7 V to 5.25 V. The ADC121S021 is packaged in 6-pin WSON and

SOT-23 package. Operation over the industrial temperature range of –40

⁰C to 85⁰C is ensured.

9.2 Functional Block Diagram

9.3 Feature Description

The ADC121S021 is fully specified over a sample rate range of 50 ksps to 200 ksps. Normal power consumption

of the device using a 3.6-V or 5.25-V supply is 1.5 mW and 7.9 mW, respectively. The power-down feature helps

reduce the power consumption to as low as 2.6 µW using a 5.25-V supply. The output serial data is straight

binary, and is compatible with several standards such as SPI, QSPI, MICROWIRE, and many common DSP

serial interfaces.

9.4 Device Functional Modes

The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal

mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is

pulled high before the 10th falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains

low. When in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time

spent in the normal and shutdown modes, a system may trade off throughput for power consumption, with a

sample rate as low as zero.

9.4.1 Normal Mode

The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no

power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th

falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device remains in normal

mode, but the current conversion aborts, and SDATA returns to TRI-STATE (truncating the output word).

Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles

have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought

high again before the start of the next conversion, which begins when CS is again brought low.

elapsed, by bringing CS low again.