1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

2

3

4

5

6

7

8

Track

Hold

Power Up

Track

Hold

b7

b6

b5

b4

b3

b2

b1

b0

b7

b6

b5

b4

b3

b2

b1

b0

9

10

DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB11 DB10

DB9

DB8

DB7

DIN

DOUT

Power Up

SCLK

CS

Power Down

Control register

Control register

ADC122S051

SNAS257E – NOVEMBER 2004 – REVISED MARCH 2013

www.ti.com

ADC122S051/ADC122S051Q Timing Specifications

(1)

Limits

Symbol

Parameter

Conditions

Typical

Units

(2)

−3.5

Setup Time SCLK High to CS Falling Edge

10

ns (min)

−0.5

+4.5

Hold time SCLK Low to CS Falling Edge

10

ns (min)

+1.5

+4

Delay from CS Until DOUT active

30

ns (max)

+2

+14.5

Data Access Time after SCLK Falling Edge

30

ns (max)

+13

Data Setup Time Prior to SCLK Rising Edge

+3

10

ns (min)

Data Valid SCLK Hold Time

+3

10

ns (min)

0.3 x

SCLK High Pulse Width

ns (min)

0.3 x

SCLK Low Pulse Width

ns (min)

1.8

Output Falling

1.3

CS Rising Edge to DOUT High-Impedance

20

ns (max)

1.0

Output Rising

1.0

(1)

PPAP (Production Part Approval Process) documentation of the device technology, process and qualification is available from Texas

Instruments upon request.

(2)

Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

(3)

Timing Diagrams

Figure 1. Operational Timing Diagram

6

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