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ADS5296ARGCR Datasheet(PDF) 1 Page - Texas Instruments |
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ADS5296ARGCR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 107 page ADS5296A www.ti.com SBAS631 – OCTOBER 2013 10-Bit, 200-MSPS, 4-Channel and 12-Bit, 80-MSPS, 8-Channel Analog-to-Digital Converter Check for Samples: ADS5296A 1 FEATURES DESCRIPTION The ADS5296A is a low-power, 12-bit, 8-channel, 2 • Configurable Modes of Operation: analog-to-digital converter (ADC) with sample rates – 10-Bit, 200-MSPS, 4-Channel ADC up to 80 MSPS. However, the device can also be – 12-Bit, 160-MSPS, 4-Channel ADC configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC – 10-Bit, 100-MSPS, 8-Channel ADC channels. In interleaving mode, the device accepts a – 12-Bit, 80-MSPS, 8-Channel ADC double frequency input clock. Each ADC in a pair • Designed for Low Power: converts a common analog input signal at alternate rising edges of the 2x input clock. The device can – 65 mW per Channel at 80 MSPS either be configured as a 10-bit, 4-channel ADC with (12-Bit, 8-Channel) sample rates up to 200 MSPS or as a 12-bit, 4- – 150 mW per Channel at 200 MSPS channel ADC with sample rates up to 160 MSPS. (10-Bit, 4-Channel) The data from each ADC within the interleaved pair is • 12-Bit, 80 MSPS: output in serial format over one LVDS pair up to a – SNR: 70.3 dBFS maximum data rate of 1 Gbps (10 bits at 100 MSPS). • 10-Bit, 200 MSPS: With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with – SNR: 61.3 dBFS sample rates up to 100 MSPS. – Interleaving Spur: > 60 dBc at 90 MHz Several digital functions commonly used in systems • Serial LVDS One-Wire Interface: are included in the device. These functions include a – 10x Serialization up to 1000 Mbps Data Rate low-frequency noise suppression (LFNS) mode, per Wire digital filtering options, and programmable mapping of LVDS output pins and analog input channels. – 12x Serialization up to 960 Mbps Data Rate per Wire For low input frequency applications, the LFNS mode • Digital Processing Block: enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by – Programmable FIR Decimation Filter and approximately 3 dB. Digital filtering options include Oversampling to Minimize Harmonic low-pass, high-pass, and band-pass digital filters as Interference well as dc offset removal filters. – Programmable IIR High-Pass Filter to Low power consumption and integration of multiple Minimize DC Offset channels in a small package makes the device – Programmable Digital Gain: 0 dB to 12 dB attractive for high channel count data acquisition • Low-Frequency Noise Suppression Mode systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is • Programmable Mapping Between ADC Input specified over the –40°C to +85°C operating Channels and LVDS Output Pins temperature range. • Channel Averaging Mode • Variety of LVDS Test Patterns to Verify Data Capture by FPGA or Receiver • Package: 9-mm × 9-mm QFN-64 APPLICATIONS • Ultrasound Imaging • Communication Applications • Multichannel Data Acquisition 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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