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ADS5444-SP Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5444-SP Datasheet(HTML) 8 Page - Texas Instruments |
8 / 22 page D4 D4 D3 D3 D2 D2 D1 D1 GND DVDD D0 D0 NC NC NC NC NC NC OVR OVR GND 60 63 59 62 58 61 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 GND DVDD GND AVDD NC NC VREF GND AVDD GND CLK CLK GND AVDD AVDD GND AIN AIN GND AVDD GND HFGPACKAGE (TOP VIEW) 79 83 78 82 77 81 76 75 80 84 74 72 71 70 73 69 68 67 66 65 64 22 41 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 42 ADS5444 ADS5444-SP SGLS391C – MARCH 2008 – REVISED JANUARY 2014 www.ti.com DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. 4, 9, 14, 15, 20, 23, AVDD 25, 27, 29, 33, 37, 39, Analog power supply 41 DVDD 2, 54, 70 Output driver power supply 1, 3, 8, 10, 13, 16, 19, 21, 22, 24, 26, 28, 30, GND Ground 32, 34, 36, 38, 40, 42, 43, 55, 64, 69 VREF 7 Reference voltage CLK 11 Differential input clock (positive). Conversion initiated on rising edge. CLK 12 Differential input clock (negative) AIN 17 Differential input signal (positive) AIN 18 Differential input signal (negative) Over range indicator LVDS output. A logic high signals an analog input in excess of the full- OVR, OVR 44, 45 scale range. D0, D0 52, 53 LVDS digital output pair, least-significant bit (LSB) D1–D4, D1–D4 56–63 LVDS digital output pairs D5–D6, D5–D6 65–68 LVDS digital output pairs 8 Submit Documentation Feedback Copyright © 2008–2014, Texas Instruments Incorporated |
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