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ADC12132 Datasheet(PDF) 3 Page - Texas Instruments |
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ADC12132 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 51 page ADC12130, ADC12132, ADC12138 www.ti.com SNAS098G – MARCH 2000 – REVISED MARCH 2013 Top View Figure 3. 28-Pin MDIP, SSOP and Wide Body SOIC Packages See Package Numbers N28B, DB0028A, and DW0028B Some of these product/package combinations are obsolete and are shown here for reference only. Check the TI web site for availability. PIN DESCRIPTIONS Pin Name Pin Description Analog Inputs to the MUX (multiplexer). A channel input is selected by the address information at the DI pin, which is loaded at the rising edge of SCLK into the address register (see Table 2 and Table 3). The voltage applied to CH0 thru CH7 these inputs should not exceed VA+ or go below VA- or below GND. Exceeding this range on an unselected channel may corrupt the reading of a selected channel. COM Analog input pin that is used as a pseudo ground when the analog multiplexer is single-ended. MUXOUT1 Multiplexer Output pins. If the multiplexer is used, these pins should be connected to the A/DIN pins, directly or MUXOUT2 through an amplifier and/of filter. Converter Input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitry A/DIN1 is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2, it may be necessary to protect these pins A/DIN2 against voltage overload. The voltage at these pins should not exceed VA + or go below AGND (see Figure 64). Data Output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-STATE. The conversion result (DB0–DB12) and converter status data are clocked out at the falling edge of SCLK on this DO pin. The word length and format of this result can vary (see Table 1). The word length and format are controlled by the data shifted into the multiplexer address and mode select register (see Table 4). Serial Data Input pin. The data applied to this pin is shifted at the rising edge of SCLK into the multiplexer address DI and mode select register. Table 2 through Table 4 show the assignment of the multiplexer address and the mode select data. This pin is an active push/pull output which indicates the status of the ADC12130/2/8.A logic low on this pin EOC indicates that the ADC is busy with a conversion, Auto Calibration, Auto Zero or power down cycle. The rising edge of EOC signals the end of one of these cycles A logic low is required at this pin to program any mode or to change the ADC's configuration as listed in Mode Programming (Table 4). When this pin is high, the ADC is placed in the read data only mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock out the data stored in the ADCs output shift register. CONV The data at DI will be ignored. A new conversion will not be started and the ADC will remain in the mode and/or configuration previously programmed. Read data only cannot be performed while a conversion, Auto Cal or Auto Zero are in progress. Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ADC12130 ADC12132 ADC12138 |
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