TIMING CHARACTERISTICS

(1) (2)

ADS5521

otherwise noted

(1)

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Input CLK falling edge to data sampling point

1

ns

Aperture jitter (uncertainty)

Uncertainty in sampling instant

300

fs

2.2

2.8

ns

50% of CLKOUT rising edge to data becoming

2.2

2.5

ns

Input clock to output data valid start,

Input clock rising edge to data valid start delay

1.9

2.8

ns

(4) (5)

Input clock to output data valid end,

Input clock rising edge to data valid end delay

5.8

7.3

ns

(4) (5)

Uncertainty in CLKOUT rising edge, peak-to-peak

175

250

2

2.2

ns

1.7

1.8

ns

Input clock rising edge, zero crossing, to output

4

4.7

5.5

ns

clock rising edge 50%

Data rise time measured from 20% to 80% of

4.4

5.1

ns

Data fall time measured from 80% to 20% of

3.3

3.8

ns

Output enable(OE) to data output delay

Time required for outputs to have stable timings

1000

Clock

cycles

Time to valid data after coming out of software

1000

power down

Clock

Wakeup time

cycles

Time to valid data after stopping and restarting the

1000

clock

Latency

Time for a sample to propagate to the ADC outputs

17.5

Clock

cycles

(1)

Timing parameters are ensured by design and characterization, and not tested in production.

(2)

See Table 6 through Table 9 in the Application Information section for timing information at additional sampling frequencies.

(3)

Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.

(4)

See the Output Information section for details on using the input clock for data capture.

(5)

These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add 1/2 clock period for the valid

number for a falling edge CLKOUT polarity.

(6)

Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect

to input clock.

6

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