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V

2

12

AV

DD

4

12

AV

5

12

AV

DD

7

12

AV

8

12

AV

DD

V

10

12

AV

DD

Production Data

ADS5541

SBAS307C – MAY 2004 – REVISED FEBRUARY 2007

A3

A2

A1

A0

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DESCRIPTION

DLL

Clock DLL

CTRL

Internal DLL is on; recommended for 60MSPS to 105MSPS

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

clock speeds.

Internal DLL is off; recommended for 2MSPS to 80MSPS

1

1

0

1

0

0

0

0

0

0

0

0

0

0

1

0

clock speeds.

TP<1>

TP<0>

Test Mode

1

1

1

0

0

0

0

0

0

0

0

0

0

0

X

0

Normal mode of operation

1

1

1

0

0

0

1

0

0

0

0

0

0

0

X

0

All outputs forced to 0

1

1

1

0

0

1

0

0

0

0

0

0

0

0

X

0

All outputs forced to 1

1

1

1

0

0

1

1

0

0

0

0

0

0

0

X

0

PDN

Power Down

1

1

1

1

0

0

0

0

0

0

0

0

0

0

X

0

Normal mode of operation

1

1

1

1

1

0

0

0

0

0

0

0

0

0

X

0

Device is put in power-down (low-current) mode.

(1)

The register contents default to the appropriate setting for normal operation up on RESET.

(2)

The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode

outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.

(3)

While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0–D13. For

example, when D0 is a 1, D1 is not assured to be a 0, and vice-versa.

Table 3. Data Format Select (DFS) Table

DATA FORMAT

CLOCK OUTPUT POLARITY

Straight Binary

Data valid on rising edge

Two's Complement

Data valid on rising edge

Straight Binary

Data valid on falling edge

Two's Complement

Data valid on falling edge

9

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