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ADS7813U Datasheet(PDF) 8 Page - Texas Instruments

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No. de pieza ADS7813U
Descripción Electrónicos  Low-Power, Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS7813U Datasheet(HTML) 8 Page - Texas Instruments

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ADS7813
8
SBAS043C
www.ti.com
STARTING A CONVERSION
If a conversion is not currently in progress, a falling edge on
the CONV input places the sample and hold into the hold
mode and begins a conversion, as shown in Figure 2 and
with the timing given in Table II. During the conversion, the
CONV input is ignored. Starting a conversion does not
depend on the state of CS. A conversion can be started once
every 25
µs (40kHz maximum conversion rate). There is no
minimum conversion rate.
Even though the CONV input is ignored while a conversion
is in progress, this input should be held static during the
conversion period. Transitions on this digital input can
easily couple into sensitive analog portions of the converter,
adversely affecting the conversion results (see the Sensitiv-
ity to External Digital Signals section of this data sheet for
more information).
Ideally, the CONV input should go LOW and remain LOW
throughout the conversion. It should return HIGH sometime
after BUSY goes HIGH. In addition, it should be HIGH
prior to the start of the next conversion for a minimum time
period given by t5. This will ensure that the digital transition
on the CONV input will not affect the signal that is acquired
for the next conversion.
An acceptable alternative is to return the CONV input HIGH
as soon after the start of the conversion as possible. For
example, a negative going pulse 100ns wide would make a
good CONV input signal. It is strongly recommended that
from time t2 after the start of a conversion until BUSY rises,
the CONV input should be held static (either HIGH or
LOW). During this time, the converter is more sensitive to
external noise.
TABLE II. ADS7813 Timing. TA = –40°C to +85°C.
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
t1
Conversion Plus Acquisition Time
25
µs
t2
CONV LOW to All Digital
8
µs
Inputs Stable
t3
CONV LOW to Initiate a Conversion
40
ns
t4
BUSY Rising to Any Digital
0
ns
Input Active
t5
CONV HIGH Prior to Start
2
µs
of Conversion
t6
BUSY LOW
19
20
µs
t7
CONV LOW to BUSY LOW
85
120
ns
t8
Aperture Delay
40
ns
t9
Conversion Time
18
20
µs
t10
Conversion Complete to
1.1
2
µs
BUSY Rising
t11
Acquisition Time
5
µs
t12
CONV LOW to Rising Edge
1.4
µs
of First DATACLK
t13
Internal DATACLK HIGH
250
350
500
ns
t14
Internal DATACLK LOW
600
760
875
ns
t15
Internal DATACLK Period
1.1
µs
t16
DATA Valid to Internal
20
ns
DATACLK Rising
t17
Internal DATACLK Falling
400
ns
to DATA Not Valid
t18
Falling Edge of Last DATACLK
800
ns
to BUSY Rising
t19
External DATACLK Rising
15
ns
to DATA Not Valid
t20
External DATACLK Rising
55
85
ns
to DATA Valid
t21
External DATACLK HIGH
50
ns
t22
External DATACLK LOW
50
ns
t23
External DATACLK Period
100
ns
t24
CONV LOW to External
100
ns
DATACLK Active
t25
External DATACLK LOW
2
µs
or CS HIGH to BUSY Rising
t26
CS LOW to Digital Outputs Enabled
85
ns
t27
CS HIGH to Digital Outputs Disabled
85
ns
Convert
Convert
Acquire
Acquire
MODE
BUSY
CONV
t
3
t
2
t
1
t
5
t
4
t
7
t
6
t
8
t
10
t
11
t
9
FIGURE 2. Basic Conversion Timing.


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