ADC08B3000 datasheet(12/57 Pages) TI1

No. de pieza	ADC08B3000

Descripción Electrónicos	High Performance, Low Power A/D Converter with 4K Buffer

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Fabricante Electrónico	TI1 [Texas Instruments]

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ADC08B3000

SNAS331M – JUNE 2006 – REVISED APRIL 2013

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Converter Electrical Characteristics

(1)(2) (continued)

The following specifications apply after calibration for VA = VDR = 1.9V, VIN FSR (a.c. coupled) = differential 810mVP-P,

CL = 10 pF, Differential a.c. coupled sine wave Input Clock, fCLK = 1.5 GHz at 0.4VP-P with 50% duty cycle, Duty Cycle

Stabilizer enabled, RCLK = 100 MHz, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog

Signal Source Impedance = 100

Ω Differential, after calibration. Boldface limits apply for TA = TMIN to TMAX. All other limits

TA = 25°C, unless otherwise noted.

Units

Parameter

Test Conditions

Typical(3)

Limits(3)

(Limits)

LVCMOS INPUT CHARACTERISTICS

ADCCLK_RST, PD, CAL

0.69 x VA

V (min)

VIH

Logic High Input Voltage

OutEdge, FSR, CalDly

0.79 x VA

V (min)

VIL

Logic Low Input Voltage

All LVCMOS Inputs

0.28 x VA

V (max)

ADCCLK_RST, CAL, PD,

1

µA

CalDly

IIH

Logic High Input Current

FSR/ECE

30

µA

ADCCLK_RST, CAL, PD,

1

µA

CalDly

IIL

Logic Low Input Current

FSR/ECE

30

µA

CIN

Input Capacitance(6)

Each input to ground

1.2

pF

LVCMOS OUTPUT CHARACTERISTICS

VOH

CMOS High level output

IOH = -400uA

1.65

1.5

V (min)

VOL

CMOS Low level output

IOH = 400uA

0.15

0.3

V (max)

POWER SUPPLY CHARACTERISTICS

Full Power Capture Mode

WEN = High,

723

800

mA (max)

REN =PD = Low

IA

Analog Supply Current

Power Down Mode

WEN = Low,

2.4

mA

REN = PD = High

Full Power Capture Mode

WEN = High,

135

180

mA (max)

REN =PD = Low

IDR

Output Driver Supply Current

Power Down Mode

WEN = Low,

10.8

mA

REN = PD = High

Full Power Capture Mode

WEN = High,

1.6

1.9

W (max)

REN =PD = Low

PD

Power Consumption

Power Down Mode

WEN = Low,

25

mW

REN = PD = High

Change in Offset Error with

PSRR1

D.C. Power Supply Rejection Ratio

70

dB

change in VA from 1.8V to 2.0V

248 MHz, 100mVP-P riding on

PSRR2

A.C. Power Supply Rejection Ratio

50

dB

VA

(6)

The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated

from the die capacitances by lead and bond wire inductances.

12

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