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ADC08DL500 Datasheet(PDF) 8 Page - Texas Instruments |
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ADC08DL500 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 57 page VDR DR GND + - + - ADC08DL500 SNAS495C – MARCH 2011 – REVISED MARCH 2011 www.ti.com Pin Functions Pin No. Symbol Equivalent Circuit Description 93 / 88 DI7 − / DQ7− 94 / 87 DI7+ / DQ7+ 95 / 86 DI6 − / DQ6− 96 / 85 DI6+ / DQ6+ 99 / 82 DI5 − / DQ5− 100 / 81 DI5+ / DQ5+ I and Q channel LVDS Data Outputs that are not delayed in 101 / 80 DI4 − / DQ4− the output demultiplexer. Compared with the DId and DQd 102 / 79 DI4+ / DQ4+ outputs, these outputs represent the later time samples. 103 / 78 DI3 − / DQ3− These outputs should always be terminated with a 100 Ω 104 / 77 DI3+ / DQ3+ differential resistor. 105 / 76 DI2 − / DQ2− 106 / 75 DI2+ / DQ2+ 114 / 67 DI1 − / DQ1− 115 / 66 DI1+ / DQ1+ 116 / 65 DI0 − / DQ0− 117 / 64 DI0+ / DQ0+ 118 / 63 DId7 − / DQd7− 119 / 62 DId7+ / DQd7+ 120 / 61 DId6 − / DQd6− 121 / 60 DId6+ / DQd6+ 125 / 56 DId5 − / DQd5− I and Q channel LVDS Data Outputs that are delayed by one 126 / 55 DId5+ / DQd5+ CLK cycle in the output demultiplexer. Compared with the 127 / 54 DId4 − / DQd4− DI/DQ outputs, these outputs represent the earlier time 128 / 53 DId4+ / DQd4+ sample. These outputs should be terminated with a 100 Ω 129 / 52 DId3 − / DQd3− differential resistor when enabled. In non-demultiplexed 130 / 51 DId3+ / DQd3+ mode, these outputs are disabled and are high impedance 131 / 50 DId2 − / DQd2− when enabled. When disabled, these outputs must be left 132 / 49 DId2+ / DQd2+ floating. 136 / 45 DId1 − / DQd1− 137 / 44 DId1+ / DQd1+ 138 / 43 DId0 − / DQd0− 139 / 42 DId0+ / DQd0+ Out Of Range output. A differential high at these pins indicates that the differential input is out of range (outside the range ±VIN/2 as programmed by the FSR pin in non-extended 89 OR+/DCLK2+ control mode or the Input Full-Scale Voltage Adjust register 90 OR-/DCLK2- setting in the extended control mode). DCLK2 is the exact mirror of DCLK and should output the same signal at the same rate. DCLK2+/- functionality: (6) Data Clock. Differential Clock outputs used to latch the output data. Delayed and non-delayed data outputs are supplied synchronous to this signal. In 1:2 demultiplexed mode, this signal is at 1/2 the input clock rate in SDR mode and at 1/4 the input clock rate in the DDR mode. By default, the DCLK outputs are not active during the termination resistor trim section of the calibration cycle. If a system requires DCLK to run continuously during a calibration cycle, the termination 92 DCLK+ resistor trim portion of the cycle can be disabled by setting 91 DCLK- the Resistor Trim Disable (RTD) bit to logic high in the Extended Configuration Register (address 9h). This disables all subsequent termination resistor trims after the initial trim which occurs during the power on calibration. Therefore, this output is not recommended as a system clock unless the resistor trim is disabled. When the device is in the non- demultiplexed mode, DCLK can only be in DDR mode and the signal is at 1/2 the input clock rate. 4, 7, 10, 15, 18, 19, 22, VA NONE Analog power supply pins. Bypass these pins to ground. 27, 30, 39, 142 46, 57, 68, Output Driver power supply pins. Bypass these pins to DR 83, 98, 113, VDR NONE GND. 124, 135 (6) This pin/bit functionality is not tested in production test; performance is tested in the specified/default mode only. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Links: ADC08DL500 |
Número de pieza similar - ADC08DL500_15 |
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Descripción similar - ADC08DL500_15 |
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