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ADS127L01IPBS Datasheet(PDF) 4 Page - Texas Instruments |
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ADS127L01IPBS Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 86 page  4 ADS127L01 SBAS607A – APRIL 2016 – REVISED MAY 2016 www.ti.com Product Folder Links: ADS127L01 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION(1) NO. NAME (2) Pull the hardware mode pins high to DVDD or low to DGND through 100-k Ω resistors. (3) See the Reset and Power-Down Pins (RESET/PWDN) section for specific hardware design details if using power-down mode. (4) Entering LP mode or VLP mode is set by REXT resistor value. 12 FILTER1 Digital input Digital filter select pin(2). 00: Wideband 1 filter (WB1) 01: Wideband 2 filter (WB2) 10 : Low-latency filter (LL) 11: Reserved 13 FILTER0 Digital input 14 FSMODE Digital input Frame-sync mode pin(2). 0: Slave mode 1: Master mode. Frame-sync mode only. 15 OSR1 Digital input Oversampling ratio (OSR) pin for the decimation filters(2). Wideband filters, FILTER[1:0] = 00 or 01: 00: 32x oversampling (OSR 32) 01: 64x oversampling (OSR 64) 10: 128x oversampling (OSR 128) 11: 256x oversampling (OSR 256) Low-latency filter, FILTER[1:0] = 10: 00: 32x oversampling (OSR 32) 01: 128x oversampling (OSR 128) 10: 512x oversampling (OSR 512) 11: 2048x oversampling (OSR 2048) 16 OSR0 Digital input 17 START Digital input Synchronization signal to start or restart a conversion. 18 DAISYIN Digital input Daisy-chain input. 19 DRDY/FSYNC Digital input/output SPI protocol: Data ready, active low(3). Frame-sync protocol: Frame-sync input signal(3) 20 DOUT Digital output Serial data output 21 DIN Digital input Serial data input. Tie directly to DGND when using the frame-sync interface. 22 SCLK Digital input/output Serial clock input(3). 23 CS Digital input Chip select. Tie directly to DGND when using the frame-sync interface. 24 CLK Digital input Master clock input. 25 CAP3 Supply output Internally-generated digital operating voltage. Connect a 1-µF capacitor to DGND. 26 DGND Digital ground Digital ground. 27 DVDD Supply input Digital supply. Decouple DVDD to DGND with a 1- μF capacitor(3) 28 RESET/PWDN Digital input Reset or power-down pin, active low(3). 29 HR Digital input ADC operating mode(2). 1: High-resolution (HR) 0: Low-power (LP) or very-low-power (VLP)(4) 30 FORMAT Digital input Interface select(2). 0: SPI 1: Frame-Sync 31 AGND Analog ground Analog ground. 32 AVDD Supply input Analog supply. Decouple AVDD to AGND with a 1- μF capacitor. |
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