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ADS1210 Datasheet(PDF) 17 Page - Texas Instruments |
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ADS1210 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 50 page  ADS1210, ADS1211 17 SBAS034B www.ti.com considerations associated with VBIAS and the settling of external circuitry. All of these must be taken into account when determining the amount of time required to resume normal operation. The timing diagram shown in Figure 10 does not take into account the settling of external circuitry. FIGURE 10. Sleep Mode to Normal Mode Timing. DRDY Serial I/O NOTE: (1) Assuming that the external circuitry has been stable for the previous three t DATA periods. t DATA One Normal Conversion (Other Modes Start Here) Data Not Valid Valid Data(1) Valid Data(1) Sleep Mode Change to Normal Mode Occurs Here ANALOG OPERATION ANALOG INPUT The input impedance of the analog input changes with ADS1210/11 clock frequency (fXIN), gain (G), and Turbo Mode Rate (TMR). The relationship is: AIN Impedance (Ω) = (10MHz/fXIN)•4.3E6/(G•TMR) Figure 11 shows the basic input structure of the ADS1210. The ADS1211 includes an input multiplexer, but this has little impact on the analysis of the input structure. The impedance is directly related to the sampling frequency of the input capacitor. The XIN clock rate sets the basic sam- pling rate in a gain of 1 and Turbo Mode Rate of 1. Higher gains and higher Turbo Mode Rates result in an increase of the sampling rate, while slower clock (XIN) frequencies result in a decrease. FIGURE 11. Analog Input Structure. R SW (8k Ω typical) Switching Frequency = f SAMP High Impedance > 1G Ω C INT 8pF Typical V CM A IN This input impedance can become a major point of consid- eration in some designs. If the source impedance of the input signal is significant or if there is passive filtering prior to the ADS1210/11, then a significant portion of the signal can be lost across this external impedance. How significant this effect is depends on the desired system performance. There are two restrictions on the analog input signal to the ADS1210/11. Under no conditions should the current into or out of the analog inputs exceed 10mA. In addition, while the analog signal must reside within this range, the linearity of the ADS1210/11 is only ensured when the actual analog input voltage resides within a range defined by AGND – 30mV and AVDD +30mV. This is due to leakage paths which occur within the part when AGND and AVDD are exceeded. For this reason, the 0V to 5V input range (gain of 1 with a 2.5V reference) must be used with caution. Should AVDD be 4.75V, the analog input signal would swing outside of the tested specifications of the device. Designs utilizing this mode of operation should consider limiting the span to a slightly smaller range. Common-mode voltages are also a significant concern in this mode and must be carefully analyzed. An input voltage range of 0.75V to 4.25V is the smallest span that is allowed if a full system calibration will be performed (see the Calibration section for more details). This also assumes an offset error of zero. A better choice would be 0.5V to 4.5V (a full-scale range of 9V). This span would allow some offset error, gain error, power supply drift, and common-mode voltage while still providing full system calibration over reasonable variation in each of these parameters. The actual input voltage exceeding AGND or AVDD should not be a concern in higher gain settings as the input voltage range will reside well within 0V to 5V. This is true unless the common-mode voltage is large enough to place positive full- scale or negative full-scale outside of the AGND to AVDD range. REFERENCE INPUT The input impedance of the REFIN input changes with clock frequency (fXIN) and Turbo Mode Rate (TMR). The relationship is: REFIN Impedance (Ω) = (10MHz/fXIN)•1E6/TMR Unlike the analog input, the reference input impedance has a negligible dependency on the PGA gain setting. The reference input voltage can vary between 2V and 3V. A nominal voltage of 2.5V appears at REFOUT, and this can be directly connected to REFIN. Higher reference voltages will cause the full-scale range to increase while the internal circuit noise of the converter remains approximately the same. This will increase the LSB weight but not the internal noise, resulting in increased signal-to-noise ratio and effec- tive resolution. Likewise, lower reference voltages will de- crease the signal-to-noise ratio and effective resolution. REFERENCE OUTPUT The ADS1210/11 contains an internal +2.5V reference. Tolerances, drift, noise, and other specifications for this reference are given in the Specification Table. Note that it is not designed to sink or to source more than 1mA of current. In addition, loading the reference with a dynamic or variable load is not recommended. This can result in small changes in reference voltage as the load changes. Finally, for designs approaching or exceeding 20 bits of effective resolution, a low-noise external reference is recommended as the internal reference may not provide adequate performance. |
Número de pieza similar - ADS1210_15 |
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Descripción similar - ADS1210_15 |
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