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ADS1210 Datasheet(PDF) 20 Page - Texas Instruments |
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ADS1210 Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 50 page  ADS1210, ADS1211 20 SBAS034B www.ti.com DF (Data Format) Bit—The DF bit controls the format of the output data, either Two’s Complement or Offset Binary, as follows: DF FORMAT ANALOG INPUT DIGITAL OUTPUT 0 Two’s +Full-Scale 7FFFFFH Default Complement Zero 000000H –Full-Scale 800000H 1 Offset Binary +Full-Scale FFFFFFH Zero 800000H –Full-scale 000000H These two formats are the same for all bits except the most significant, which is simply inverted in one format vs the other. This bit only applies to the Data Output Register—it has no effect on the other registers. U/B (Unipolar) Bit—The U/B bit controls the limits im- posed on the output data, as follows: U/B MODE LIMITS 0 Bipolar None Default 1 Unipolar Zero to +Full-Scale only The particular mode has no effect on the actual full-scale range of the ADS1210/11, data format, or data format vs input voltage. In the bipolar mode, the ADS1210/11 oper- ates normally. In the unipolar mode, the conversion result is limited to positive values only (zero included). This bit only controls what is placed in the Data Output Register. It has no effect on internal data. When cleared, the very next conversion will produce a valid bipolar result. BD (Byte Order) Bit—The BD bit controls the order in which bytes of data are read, either most significant byte first or least significant byte, as follows: SDL (Serial Data Line) Bit—The SDL bit controls which pin on the ADS1210/11 will be used as the serial data output pin, either SDIO or SDOUT, as follows: The MSB bit only affects read operations; it has no effect on write operations. SDL SERIAL DATA OUTPUT PIN 0 SDIO Default 1 SDOUT If SDL is LOW, then SDIO will be used for both input and output of serial data—see the Timing section for more details on how the SDIO pin transitions between these two states. In addition, SDOUT will remain in a tri-state condi- tion at all times. Important Note: Since the default condition is SDL LOW, SDIO has the potential of becoming an output once every data output cycle if the ADS1210/11 is in the Master Mode. This will occur until the Command Register can be written and the SDL bit set HIGH. See the Interfacing section for more information. DRDY (Data Ready) Bit—The DRDY bit is a read-only bit which reflects the state of the ADS1210/11’s DRDY output pin, as follows: DRDY MEANING 0 Data Ready 1 Data Not Ready DSYNC (Data Synchronization) Bit—The DSYNC bit is a write-only bit which occupies the same location as DRDY. When a ‘one’ is written to this location, the effect on the ADS1210/11 is the same as if the DSYNC input pin had been taken LOW and returned HIGH. That is, the modulator count for the current conversion cycle will be reset to zero. The DSYNC bit is provided in order to reduce the number of interface signals that are needed between the ADS1210/11 and the main controller. Consult “Making Use of DSYNC” in the Serial Interface section for more information. MD2-MD0 (Operating Mode) Bits—The MD2-MD0 bits initiate or enable the various calibration sequences, as follows: DSYNC MEANING 0 No Change in Modulator Count 1 Modulator Count Reset to Zero MD2 MD1 MD0 OPERATING MODE 0 0 0 Normal Mode 0 0 1 Self-Calibration 0 1 0 System Offset Calibration 0 1 1 System Full-Scale Calibration 1 0 0 Pseudo System Calibration 1 0 1 Background Calibration 1 1 0 Sleep 1 1 1 Reserved The Normal Mode, Background Calibration Mode, and Sleep Mode are permanent modes and the ADS1210/11 will remain in these modes indefinitely. All other modes are temporary and will revert to Normal Mode once the appro- priate actions are complete. See the Calibration and Sleep Mode sections for more information. BD BYTE ACCESS ORDER 0 Most Significant Default to Least Significant Byte 1 Least Significant to Most Significant Byte Note that when BD is clear and a multi-byte read is initiated, A3-A0 of the Instruction Register is the address of the most significant byte and subsequent bytes reside at higher ad- dresses. If BD is set, then A3-A0 is the address of the least significant byte and subsequent bytes reside at lower ad- dresses. The BD bit only affects read operations; it has no effect on write operations. MSB (Bit Order) Bit—The MSB bit controls the order in which bits within a byte of data are read, either most significant bit first or least significant bit, as follows: MSB BIT ORDER 0 Most Significant Bit First Default 1 Least Significant Bit First |
Número de pieza similar - ADS1210_15 |
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Descripción similar - ADS1210_15 |
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