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ADS1210 Datasheet(PDF) 21 Page - Texas Instruments |
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ADS1210 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 50 page  ADS1210, ADS1211 21 SBAS034B www.ti.com DATA DECI- RATE MATION (HZ) RATIO DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1000 19 0000 0 0 0 0 100 11 500 38 0000 0 0 0 1 001 10 250 77 0000 0 0 1 0 011 01 100 194 0000 0 1 1 0 000 10 60 325 0000 1 0 1 0 001 01 50 390 0000 1 1 0 0 001 10 20 976 0001 1 1 1 0 100 00 10 1952 0011 1 1 0 1 000 00 Table XI. Decimation Ratios vs Data Rates (Turbo Mode rate of 1 and 10MHz clock). CH1 CH0 ACTIVE INPUT 0 0 Channel 1 Default 0 1 Channel 2 1 0 Channel 3 1 1 Channel 4 TURBO AVAILABLE MODE PGA SF2 SF1 SF0 RATE SETTINGS 0001 1, 2, 4, 8, 16 Default 0012 1, 2, 4, 8 0104 1, 2, 4 0118 1, 2 100 16 1 Most Significant Bit Byte 2 DOR23 DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16 Byte 1 DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR9 DOR8 Byte 0 Least Significant Bit DOR7 DOR6 DOR5 DOR4 DOR3 DOR2 DOR1 DOR0 TABLE XII. Data Output Register. G2-G0 (PGA Control) Bits—The G2-G0 bits control the gain setting of the PGA, as follows: GAIN AVAILABLE TURBO G2 G1 G0 SETTING MODE RATES 0 0 0 1 1, 2, 4, 8, 16 Default 0 0 1 2 1, 2, 4, 8 0 1 0 4 1, 2, 4 011 8 1, 2 100 16 1 The gain is partially implemented by increasing the input capacitor sampling frequency, which is given by the follow- ing equation: fSAMP = G • TMR • fXIN/512 where G is the gain setting and TMR is the Turbo Mode Rate. The product of G and TMR cannot exceed 16. The sampling frequency of the input capacitor directly relates to the analog input impedance. See the Programmable Gain Amplifier and Analog Input sections for more details. CH1-CH0 (Channel Selection) Bits—The CH1 and CH0 bits control the input multiplexer on the ADS1211, as follows: (For the ADS1210, CH1 and CH0 must always be zero.) The channel change takes effect when the last bit of byte 2 has been written to the Command Register. Output data will not be valid for the next three conversions despite the DRDY signal indicating that data is ready. On the fourth time that DRDY goes LOW after a channel change has been written to the Command Register, valid data will be present in the Data Output Register (see Figure 4). SF2-SF0 (Turbo Mode Rate) Bits—The SF2-SF0 bits control the input capacitor sampling frequency and modula- tor rate, as follows: The input capacitor sampling frequency and modulator rate can be calculated from the following equations: fSAMP = G • TMR • fXIN/ 512 fMOD = TMR • fXIN/512 where G is the gain setting and TMR is the Turbo Mode Rate. The sampling frequency of the input capacitor directly relates to the analog input impedance. The modulator rate relates to the power consumption of the ADS1210/11 and the output data rate. See the Turbo Mode, Analog Input, and Reference Input sections for more details. DR12-DR0 (Decimation Ratio) Bits—The DR12-DR0 bits control the decimation ratio of the ADS1210/11. In essence, these bits set the number of modulator results which are used in the digital filter to compute each individual conversion result. Since the modulator rate depends on both the ADS1210/11 clock frequency and the Turbo Mode Rate, the actual output data rate is given by the following equation: fDATA = fXIN • TMR / (512 • (Decimation Ratio + 1)) where TMR is the Turbo Mode Rate. Table XI shows various data rates and corresponding decimation ratios (with a 10MHz clock). Valid decimation ratios are from 19 to 8000. Outside of this range, the digital filter will compute results incorrectly due to inadequate or too much data. Data Output Register (DOR) The DOR is a 24-bit register which contains the most recent conversion result (see Table XII). This register is updated with a new result just prior to DRDY going LOW. If the contents of the DOR are not read within a period of time defined by 1/fDATA –12•(1/fXIN), then a new conversion result will overwrite the old. (DRDY is forced HIGH prior to the DOR update, unless a read is in progress). The contents of the DOR can be in Two’s Complement or Offset Binary format. This is controlled by the DF bit of the Command Register. In addition, the contents can be limited to unipolar data only with the U/B bit of the Command Register. |
Número de pieza similar - ADS1210_15 |
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Descripción similar - ADS1210_15 |
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