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ADS1210 Datasheet(PDF) 23 Page - Texas Instruments

No. de pieza ADS1210
Descripción Electrónicos  24-Bit ANALOG-TO-DIGITAL CONVERTER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1210 Datasheet(HTML) 23 Page - Texas Instruments

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TABLE XV. Digital Timing Characteristics.
SYMBOL
DESCRIPTION
MIN
NOM
MAX
UNITS
fXIN
XIN Clock Frequency
0.5
10
MHz
tXIN
XIN Clock Period
100
2000
ns
t2
XIN Clock High
0.4 • tXIN
ns
t3
XIN Clock LOW
0.4 • tXIN
ns
t4
Internal Serial Clock HIGH
tXIN
ns
t5
Internal Serial Clock LOW
tXIN
ns
t6
Data In Valid to Internal SCLK Falling Edge (Setup)
40
ns
t7
Internal SCLK Falling Edge to Data In Not Valid (Hold)
20
ns
t8
Data Out Valid to Internal SCLK Falling Edge (Setup)
tXIN –25
ns
t9
Internal SCLK Falling Edge to Data Out Not Valid (Hold)
tXIN
ns
t10
External Serial Clock HIGH
2.5 • tXIN
ns
t11
External Serial Clock LOW
2.5 • tXIN
ns
t12
Data In Valid to External SCLK Falling Edge (Setup)
40
ns
t13
External SCLK Falling Edge to Data In Not Valid (Hold)
20
ns
t14
Data Out Valid to External SCLK Falling Edge (Setup)
tXIN –40
ns
t15
External SCLK Falling Edge to Data Out Not Valid (Hold)
1.5 • tXIN
ns
t16
Falling Edge of DRDY to First SCLK Rising Edge
6 • tXIN
ns
(Master Mode, CS Tied LOW)
t17
Falling Edge of Last SCLK for INSR to Rising Edge of First
5 • tXIN
ns
SCLK for Register Data (Master Mode)
t18
Falling Edge of Last SCLK for Register Data to Rising Edge
3 • tXIN
ns
of DRDY (Master Mode)
t19
Falling Edge of Last SCLK for INSR to Rising Edge of First
5.5 • tXIN
ns
SCLK for Register Data (Slave Mode)
ns
t20
Falling Edge of Last SCLK for Register Data to Rising Edge
4 • tXIN
5 • tXIN
ns
of DRDY (Slave Mode)
t21
Falling Edge of DRDY to Falling Edge of CS (Master and
0.5 • tXIN
ns
Slave Mode)
t22
Falling Edge of CS to Rising Edge of SCLK (Master Mode)
5 • tXIN
6 • tXIN
ns
t23
Rising Edge of DRDY to Rising Edge of CS (Master and
10
ns
Slave Mode)
t24
Falling Edge of CS to Rising Edge of SCLK (Slave Mode)
5.5 • tXIN
ns
t25
Falling Edge of Last SCLK for INSR to SDIO Tri-state
2 • tXIN
ns
(Master Mode)
t26
SDIO as Output to Rising Edge of First SCLK for Register
2 • tXIN
ns
Data (Master and Slave Modes)
t27
Falling Edge of Last SCLK for INSR to SDIO Tri-state
3 • tXIN
4 • tXIN
ns
(Slave Mode)
t28
SDIO Tri-state Time (Master and Slave Modes)
tXIN
ns
t29
Falling Edge of Last SCLK for Register Data to SDIO Tri-State
tXIN
ns
(Master Mode)
t30
Falling Edge of Last SCLK for Register Data to SDIO
2 • tXIN
3 • tXIN
ns
Tri-state (Slave Mode)
t31
DRDY Fall Time
30
ns
t32
DRDY Rise Time
30
ns
t33
Minimum DSYNC LOW Time
10.5 • tXIN
ns
t34
DSYNC Valid HIGH to Falling Edge of XIN (for Exact
10
ns
Synchronization of Multiple Converters only)
t35
Falling Edge of XIN to DSYNC Not Valid LOW (for Exact
10
ns
Synchronization of Multiple Converters only)
t36
Falling Edge of Last SCLK for Register Data to Rising Edge
20.5 • tXIN
ns
of First SCLK of next INSR (Slave Mode, CS Tied LOW)
t37
Rising Edge of CS to Falling Edge of CS (Slave Mode,
10.5 • tXIN
ns
Using CS)
t38
Falling Edge of DRDY to First SCLK
5.5 • tXIN
ns
Rising Edge (Slave Mode, CS Tied LOW)


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