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ADS1210 Datasheet(PDF) 27 Page - Texas Instruments

No. de pieza ADS1210
Descripción Electrónicos  24-Bit ANALOG-TO-DIGITAL CONVERTER
Download  50 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1210 Datasheet(HTML) 27 Page - Texas Instruments

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ADS1210, ADS1211
27
SBAS034B
www.ti.com
Start
Writing
ADS1210/11
drives DRDY LOW
CS
state
ADS1210/11
generates 8
serial clock cycles
and receives
Instruction Register
data via SDIO
ADS1210/11
generates n
serial clock cycles
and receives
specified
register data
via SDIO
ADS1210/11
drives DRDY HIGH
End
ADS1210/11
generates 8 serial clock
cycles and receives
Instruction Register
data via SDIO
ADS1210/11 generates n
serial clock cycles
and transmits specified
register data via SDOUT
End
Start
Reading
ADS1210/11
drives DRDY LOW
CS
state
Continuous
Read
Mode?
ADS1210/11
drives DRDY HIGH
SDOUT returns to
tri-state condition
SDOUT becomes
active from tri-state
Use
SDIO for
output?
HIGH
No
Yes
LOW
HIGH
No
Yes
ADS1210/11 generates n
serial clock cycles
and transmits specified
register data via SDIO
SDIO transitions to
tri-state condition
SDIO input to
output transition
CS
state
LOW
LOW
HIGH
For example, Figure 24 shows that just prior to the DRDY
signal going LOW, the internal Data Output Register (DOR)
is updated. This update involves the Offset Calibration
Register (OCR) and the Full-Scale Register (FSR). If the
OCR or FSR are being written, their final value may not be
correct, and the result placed into the DOR will certainly not
be valid. Problems can also arise if certain bits of the
Command Register are being changed.
Note that reading the Data Output Register is an excep-
tion. If the DOR is being read when the internal update is
initiated, the update is blocked. The old output data will
remain in the DOR and the new data will be lost. The old
data will remain valid until the read operation has com-
pleted. In general, multiple instructions may be issued, but
the last one in any conversion period should be complete
within 12 • XIN clock periods of the next DRDY LOW
time. In this usage, “complete” refers to the point where
DRDY rises in Figures 17 and 19 (in the Timing Section).
Consult Figures 25 and 26 for the flow of serial data
during any one conversion period.
FIGURE 25. Flowchart for Writing and Reading Register Data, Master Mode.


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