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ADS1210 Datasheet(PDF) 30 Page - Texas Instruments |
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ADS1210 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 50 page  ADS1210, ADS1211 30 SBAS034B www.ti.com If a serial communication does not occur during any conver- sion period, the ADS1210/11 will continue to operate prop- erly. However, the results in the Data Output Register will be lost when they are overwritten by the new result at the start of the next conversion period. Just prior to this update, DRDY will be forced HIGH and will return LOW after the update. Making Use of DSYNC The DSYNC input pin and the DSYNC write bit in the Command Register reset the current modulator count to zero. This causes the current conversion cycle to proceed as normal, but all modulator outputs from the last data output to the point where DSYNC is asserted are discarded. Note that the previous two data outputs are still present in the ADS1210/11 internal memory. Both will be used to com- pute the next conversion result, and the most recent one will be used to compute the result two conversions later. DSYNC does not reset the internal data to zero. There are two main uses of DSYNC. In the first case, DSYNC allows for synchronization of multiple converters. In regards to the DSYNC input pin, this case was discussed under “Synchronizing Multiple Converters” in the Timing section. In regards to the DSYNC bit, it will be difficult to set all of the converter’s DSYNC bits at the same time unless all of the converters are in the Slave Mode and the same instruction can be sent to all of the converters at the same time. The second use of DSYNC is to reset the modulator count to zero in order to obtain valid data as quickly as possible. For example, if the input channel is changed on the ADS1211, the current conversion cycle will be a mix of the old channel and the new channels. Thus, four conversions are needed in order to ensure valid data. However, if the channel is changed and then DSYNC is used to reset the modulator count, the modulator data at the end of the current conver- sion cycle will be entirely from the new channel. After two additional conversion cycles, the output data will be com- pletely valid. Note that the conversion cycle in which DSYNC is used will be slightly longer than normal. Its length will depend on when DSYNC was set. Reset, Power-On Reset, and Brown-Out The ADS1210/11 contains an internal power-on reset circuit. If the power supply ramp rate is greater than 50mV/ms, this circuit will be adequate to ensure that the device powers up correctly. (Due to oscillator settling considerations, commu- nication to and from the ADS1210/11 should not occur for at least 25ms after power is stable.) If this requirement cannot be met or if the circuit has brown-out considerations, the timing diagram of Figure 27 can be used to reset the ADS1210/11. This timing applies only when the ADS1210/11 is in the Slave Mode and accomplishes the reset by controlling the duty cycle of the SCLK input. In general, a reset is required after power-up, after a brown-out has been detected, or when a watchdog timer event has occured. If the ADS1210/11 is in the Master Mode, a reset of the device is not possible. If the power supply does not meet the minimum ramp rate requirement, or brown-out is of concern, low on-resistance MOSFETs or equivalent should be used to control power to the ADS1210/11. When powered down, the device should be left unpowered for at least 300ms before power is reapplied. An alternate method would be to control the MODE pin and temporarily place the ADS1210/11 in the Slave Mode while a reset is initiated as shown in Figure 27. Two-Wire Interface For a two-wire interface, the Master Mode of operation may be preferable. In this mode, serial communication occurs only when data is ready, informing the main controller as to the status of the ADS1210/11. The disadvantages are that the ADS1210/11 must have a dedicated serial port on the main controller, only one instruction can be issued per data ready period, and the serial clock may define the maximum clock frequency of the converter. In the Slave Mode, the main controller must read and write to the ADS1210/11 “blindly.” Writes to the internal regis- ters, such as the Command Register or Offset Calibration Register, might occur during an update of the Data Output Register. This can result in invalid data in the DOR. A two- wire interface can be used if the main controller can read and/or write to the converter, either much slower or much faster that the data rate. For example, if much faster, the main controller can use the DRDY bit to determine when data is becoming valid (polling it multiple times during one conversion cycle). Thus, the controller obtains some idea of when to write to the internal register. If much slower, then reads of the DOR might always return valid data (multiple conversions have occurred since the last read of the DOR or since any write of the internal registers). FIGURE 27. Resetting the ADS1210/11 (Slave Mode only). t1: > 256 • tXIN < 400 • tXIN t2:> 5 • tXIN t3: > 512 • tXIN < 900 • tXIN t4: ≥ 1024 • tXIN < 1200 • tXIN t 1 t 3 t 4 t 2 t 2 SCLK Reset Occurs at Falling Edge |
Número de pieza similar - ADS1210_15 |
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Descripción similar - ADS1210_15 |
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