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ADS1210 Datasheet(PDF) 12 Page - Texas Instruments

No. de pieza ADS1210
Descripción Electrónicos  24-Bit ANALOG-TO-DIGITAL CONVERTER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1210 Datasheet(HTML) 12 Page - Texas Instruments

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ADS1210, ADS1211
12
SBAS034B
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Filter Equation
The digital filter is described by the following transfer
function:
where N is the Decimation Ratio.
This filter has a (sin(x)/x)3 response and is referred to a sinc3
filter. For the ADS1210/11, this type of filter allows the data
rate to be changed over a very wide range (nearly four orders
of magnitude). However, the –3dB point of the filter is 0.262
times the data rate. And, as can be seen in Figures 1 and 2,
the rejection in the stopband (frequencies higher than the
first notch frequency) may only be –40dB.
These factors must be considered in the overall system
design. For example, with a 50Hz data rate, a significant
signal at 75Hz may alias back into the passband at 25Hz.
The analog front end can be designed to provide the needed
attenuation to prevent aliasing, or the system may simply
provide this inherently. Another possibility is increasing the
data rate and then post filtering with a digital filter on the
main controller.
Filter Settling
The number of modulator results used to compute each
conversion result is three times the Decimation Ratio. This
means that any step change (or any channel change for the
ADS1211) will require at least three conversions to fully
settle. However, if the change occurs asynchronously, then at
least four conversions are required to ensure complete set-
tling. For example, on the ADS1211, the fourth conversion
result after a channel change will be valid (see Figure 4).
|H (f ) |
=
sin
π• f • N
f
MOD


N
• sin π•
f
f
MOD


3
the effective resolution of the output data at a given data rate,
but there is also an increase in power dissipation. For Turbo
Mode Rates 2 and 4, the increase is slight. For rates 8 and
16, the increase is more substantial. See the Typical Perfor-
mance Curves for more information.
In a Turbo Mode Rate of 16, the ADS1210/11 can offer 20
bits of effective resolution at a 1kHz data rate. A comparison
of effective resolution versus Turbo Mode Rates and output
data rates is shown in Table IV while Table V shows the
corresponding noise level in
µVrms.
TURBO MODE
The ADS1210/11 offers a unique Turbo Mode feature which
can be used to increase the modulator sampling rate by 2, 4,
8, or 16 times normal. With the increase of modulator
sampling frequency, there can be a substantial increase in
DATA
TURBO
TURBO
TURBO
TURBO
TURBO
RATE
MODE
MODE
MODE
MODE
MODE
(HZ)
RATE 1
RATE 2
RATE 4
RATE 8
RATE 16
10
21.5
22.0
22.5
20
21.0
22.0
22.0
22.5
40
20.0
21.5
22.0
22.5
23.0
50
20.0
21.5
21.5
22.0
23.0
60
19.5
21.0
21.5
22.0
23.0
100
18.0
20.0
21.0
21.5
22.5
1000
10.0
12.5
15.0
17.5
20.0
EFFECTIVE RESOLUTION (BITS RMS)
TABLE IV. Effective Resolution vs Data Rate and Turbo Mode
Rate. (Gain setting of 1 and 10MHz clock.)
DATA
TURBO
TURBO
TURBO
TURBO
TURBO
RATE
MODE
MODE
MODE
MODE
MODE
(Hz)
RATE 1
RATE 2
RATE 4
RATE 8
RATE 16
10
2.9
1.7
1.3
20
4.3
2.1
1.7
1.3
40
6.9
3.0
2.3
1.6
1.0
50
8.1
3.2
2.4
1.8
1.0
60
10.5
3.9
2.6
1.9
1.0
100
26.9
6.9
3.5
2.7
1.4
1000
6909.7
1354.5
238.4
46.6
7.8
TABLE V. Noise Level vs Data Rate and Turbo Mode Rate.
(Gain setting of 1 and 10MHz clock.)
NOISE LEVEL (
µVrms)
The Turbo Mode feature allows trade-offs to be made
between the ADS1210/11 XIN clock frequency, power dissi-
pation, and effective resolution. If a 5MHz clock is available
but a 10MHz clock is needed to achieve the desired perfor-
mance, a Turbo Mode Rate of 2X will result in the same
effective resolution. Table VI provides a comparison of
effective resolution at various clock frequencies, data rates,
and Turbo Mode Rates.
DATA
XIN CLOCK
TURBO
EFFECTIVE
RATE
FREQUENCY
MODE
RESOLUTION
(Hz)
(MHz)
RATE
(Bits rms)
60
10
1
19.5
60
5
2
19.5
60
2.5
4
19.5
60
1.25
8
19.5
60
0.625
16
19.5
100
10
1
18.0
100
5
2
18.0
100
2.5
4
18.0
100
1.25
8
18.0
100
0.625
16
18.0
TABLE VI. Effective Resolution vs Data Rate, Clock
Frequency, and Turbo Mode Rate. (Gain set-
ting of 1.)
FIGURE 4. Asynchronous ADS1210/11 Analog Input Volt-
age Step or ADS1211 Channel Change to Fully
Settled Output Data.
DRDY
Serial
I/O
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Data
not
Valid
Data
not
Valid
Data
not
Valid
Significant Analog Input Change
or
ADS1211 Channel Change
t
DATA


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