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ADS1210 Datasheet(PDF) 15 Page - Texas Instruments

No. de pieza ADS1210
Descripción Electrónicos  24-Bit ANALOG-TO-DIGITAL CONVERTER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1210 Datasheet(HTML) 15 Page - Texas Instruments

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ADS1210, ADS1211
15
SBAS034B
www.ti.com
Normal
Mode
Background Calibration
Mode
Valid
Data
DRDY
Serial
I/O
Valid
Data
BC(1)
t
DATA
Offset
Calibration on
Internal Offset(2)
Analog
Input
Conversion
Analog
Input
Conversion
Cycle Repeats
with Offset
Calibration
Full-Scale
Calibration on
Internal Full-Scale
NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset
calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles.
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the full-scale calibra-
tion is performed. In this case, the digital filter already
contains a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. The calibration
error will be a sum of the rms noise on the conversion result
and the input signal noise. See the System Calibration Limits
section for information regarding the limits on the magni-
tude of the system full-scale voltage.
Pseudo System Calibration
The Pseudo System Calibration is performed after the bits
100 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 8). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed
on the differential input voltage present at the converter’s
input over the next three conversion periods (four in Slave
Mode). Then, the input to the sampling capacitor is discon-
nected from the converter’s analog input and connected
across REFIN. A gain calibration is performed over the next
three conversions.
After this, the Operation Mode bits are reset to 000 (normal
mode) and the input capacitor is then reconnected to the
FIGURE 8. Pseudo System Calibration Timing.
FIGURE 9. Background Calibration Timing.
Valid
Data
DRDY
Serial
I/O
Valid
Data
PSC(1)
t
DATA
Normal
Mode
Valid
Data
Valid
Data
Normal
Mode
Offset
Calibration on
System Offset(2)
Pseudo System
Calibration Mode
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
input. Conversions proceed as usual over the next three
cycles in order to fill the digital filter. DRDY remains
HIGH during this time. On the next cycle, the DRDY signal
goes LOW indicating valid data and resumption of normal
operation.
The system offset calibration range of the ADS1210/11
is limited and is listed in the Specifications Table. For
more information on how to use these specifications, see
the System Calibration Limits section. To calculate VOS,
use 2 • REFIN /GAIN for VFS.
Background Calibration
The Background Calibration Mode is entered after the bits
101 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
continuous sequence (see Figure 9). At the start of the next
conversion cycle, the DRDY signal will not go LOW but
will remain HIGH. The inputs to the sampling capacitor are
disconnected from the converter’s analog input and shorted
together. An offset calibration is performed over the next
three conversion periods (in Slave Mode, the very first offset
calibration requires four periods and all subsequent offset
calibrations require three periods). Then, the input capacitor
is reconnected to the input. Conversions proceed as usual
over the next three cycles in order to fill the digital filter.
DRDY remains HIGH during this time. On the next cycle,
the DRDY signal goes LOW indicating valid data.


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