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ADS8341EBG4 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS8341EBG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 24 page  ADS8341 11 SBAS136D THEORY OF OPERATION The ADS8341 is a classic Successive Approximation Reg- ister (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sample- and-hold function. The converter is fabricated on a 0.6 µm CMOS process. The basic operation of the ADS8341 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 500mV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS8341. The analog input to the converter is differential and is provided via a four-channel multiplexer. The input can be provided in reference to a voltage on the COM pin (which is generally ground) or differentially by using two of the four input channels (CH0 - CH3). The particular configuration is selectable via the digital interface. ANALOG INPUT Figure 2 shows a block diagram of the input multiplexer on the ADS8341. The differential input of the converter is derived from one of the four inputs in reference to the COM pin or two of the four inputs. Table I and Table II show the relationship between the A2, A1, A0, and SGL/DIF control bits and the configuration of the analog multiplexer. The control bits are provided serially via the DIN pin, see the Digital Interface section of this data sheet for more details. When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs, as shown in Figure 2, is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.2V and 1.25V, allowing the input to reject small signals that are common to both the +IN and –IN input. The +IN input has a range of –0.2V to +VCC + 0.2V. FIGURE 2. Simplified Diagram of the Analog Input. A2 A1 A0 CH0 CH1 CH2 CH3 COM 001 +IN –IN 101 –IN +IN 010 +IN –IN 110 –IN +IN TABLE II. Differential Channel Control (SGL/DIF LOW). A2 A1 A0 CH0 CH1 CH2 CH3 COM 001 +IN –IN 101 +IN –IN 010 +IN –IN 110 +IN –IN TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH). The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typi- cally 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conver- sion rate. FIGURE 1. Basic Operation of the ADS8341. Converter +IN –IN CH0 CH1 CH2 CH3 COM A2-A0 (Shown 001 B) SGL/DIF (Shown HIGH) +V CC CH0 CH1 CH2 CH3 COM SHDN V REF 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DCLK CS DIN BUSY DOUT GND GND +V CC Serial/Conversion Clock Chip Select Serial Data In Serial Data Out 0.1 µF1µF 0.1 µF +2.7V to +5V ADS8341 Single-ended or differential analog inputs + + 1 µF to 10 µF External V REF |
Número de pieza similar - ADS8341EBG4 |
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Descripción similar - ADS8341EBG4 |
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