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ADS8330IBPWR Datasheet(PDF) 9 Page - Texas Instruments |
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ADS8330IBPWR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 50 page TIMING CHARACTERISTICS ADS8329 ADS8330 www.ti.com ................................................................................................................................................... SLAS516C – DECEMBER 2006 – REVISED JULY 2009 All specifications typical at –40°C to 85°C, +VA = 2.7 V, +VBD = 1.8 V (unless otherwise noted) (1) (2) PARAMETER MIN TYP MAX UNIT External, 3 V ≤ +VA ≤ 3.6 V, 0.5 21 fCCLK = 1/2 fSCLK External, 2.7 V ≤ +VA ≤ 3 V, fCCLK Frequency, conversion clock, CCLK 0.5 18.9 MHz fCCLK = 1/2 fSCLK Internal, 20 22.3 23.5 fCCLK = 1/2 fSCLK tsu(CSF-EOC) Setup time, falling edge of CS to EOC 1 CCLK th(CSF-EOC) Hold time, falling edge of CS to EOC 0 ns twL(CONVST) Pulse duration, CONVST low 40 ns tsu(CSF-EOS) Setup time, falling edge of CS to EOS 20 ns th(CSF-EOS) Hold time, falling edge of CS to EOS 20 ns tsu(CSR-EOS) Setup time, rising edge of CS to EOS 20 ns th(CSR-EOS) Hold time, rising edge of CS to EOS 20 ns Setup time, falling edge of CS to first tsu(CSF-SCLK1F) 5 ns falling SCLK twL(SCLK) Pulse duration, SCLK low 8 tc(SCLK) – 8 ns twH(SCLK) Pulse duration, SCLK high 8 tc(SCLK) – 8 ns All modes, 23.8 2000 3 V ≤ +VA ≤ 3.6 V tc(SCLK) Cycle time, SCLK ns All modes, 26.5 2000 2.7 V ≤ +VA < 3 V Delay time, falling edge of SCLK to SDO td(SCLKF-SDOINVALID) 10-pF Load 7.5 ns invalid Delay time, falling edge of SCLK to SDO td(SCLKF-SDOVALID) 10-pF Load 16 ns valid 10-pF Load, 13 2.7 V ≤ +VA ≤ 3 V Delay time, falling edge of CS to SDO td(CSF-SDOVALID) ns valid, SDO MSB output 10-pF Load, 11 3 V ≤ +VA ≤ 3.6 V tsu(SDI-SCLKF) Setup time, SDI to falling edge of SCLK 8 ns th(SDI-SCLKF) Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO td(CSR-SDOZ) 8 ns 3-state Setup time, 16th falling edge of SCLK tsu(16th SCLKF-CSR) 10 ns before rising edge of CS/FS Delay time, CDI high to SDO high in td(SDO-CDI) 10-pF Load, chain mode 23 ns daisy chain mode (1) All input signals are specified with tr = tf = 1.5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): ADS8329 ADS8330 |
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