54ACT16657, 74ACT16657

16-BIT TRANSCEIVERS

WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

SCAS164A – JANUARY 1991 – REVISED APRIL 1996

2

POST OFFICE BOX 655303

description (continued)

In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR)

output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example,

if 1ODD/EVEN is high (odd parity selected), 1PARITY is high, and there are three high bits on the 1B bus, then

1ERR is low, indicating a parity error.

The 74ACT16657 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and

functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16657 is characterized for operation over the full military temperature range of –55

°C to 125°C. The

74ACT16657 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

NUMBER OF A OR B

INPUTS

INPUT/OUTPUT

OUTPUTS

NUMBER OF A OR B

INPUTS THAT ARE HIGH

OE

T/R

ODD/EVEN

INPUT/OUTPUT

PARITY

ERR

OUTPUT MODE

L

H

H

H

Z

Transmit

L

HL

L

Z

Transmit

02468

L

LH

H

H

Receive

0, 2, 4, 6, 8

L

LH

L

L

Receive

L

LL

H

L

Receive

L

LL

L

H

Receive

L

H

H

L

Z

Transmit

L

HL

H

Z

Transmit

1357

L

LH

H

L

Receive

1, 3, 5, 7

L

LH

L

H

Receive

L

LL

H

H

Receive

L

LL

L

L

Receive

Don’t care

H

X

X

Z

Z

Z